Unified Coverage Report :: Group :: tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

Group : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv

---

Summary for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	99	0	99	100.00

Variables for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
read_interval	99	0	99	100.00	100	1	1	0

Summary for Variable read_interval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	99	0	99	100.00

User Defined Bins for read_interval

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5037688	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
duration[1]	407997	1		T7	5		T31	2002		T50	23
duration[2]	714870	1		T4	38		T19	238		T49	203
duration[3]	120168	1		T4	1		T6	1		T7	43
duration[4]	991551	1		T3	512		T4	59		T5	1172
duration[5]	66302	1		T6	3		T7	5		T31	390
duration[6]	472116	1		T3	216		T4	1		T5	1736
duration[7]	50831	1		T3	402		T4	1		T7	3
duration[8]	27695	1		T4	1		T7	1		T25	1
duration[9]	35961	1		T4	7		T5	1		T31	214
duration[10]	22194	1		T4	2		T31	65		T51	1
duration[11]	24547	1		T4	3		T6	1		T31	106
duration[12]	23598	1		T4	1		T6	2		T8	1
duration[13]	20172	1		T4	2		T6	1		T25	1
duration[14]	20441	1		T4	6		T31	56		T52	13
duration[15]	17372	1		T4	4		T31	30		T52	1
duration[16]	17281	1		T31	36		T52	4		T32	13
duration[17]	17967	1		T4	4		T19	1		T31	18
duration[18]	15183	1		T4	2		T21	1		T31	27
duration[19]	16195	1		T21	1		T25	1		T31	14
duration[20]	15526	1		T4	4		T21	5		T7	9
duration[21]	14008	1		T6	1		T7	3		T31	9
duration[22]	14420	1		T21	9		T6	2		T7	16
duration[23]	10791	1		T4	1		T21	2		T7	2
duration[24]	11461	1		T4	1		T21	7		T25	2
duration[25]	10644	1		T4	1		T21	1		T49	51
duration[26]	9926	1		T4	1		T19	5		T21	4
duration[27]	5983	1		T19	4		T21	1		T31	8
duration[28]	5481	1		T19	8		T21	2		T31	6
duration[29]	4966	1		T4	1		T5	1		T21	1
duration[30]	3759	1		T31	4		T50	7		T52	9
duration[31]	3714	1		T5	1		T31	2		T50	14
duration[32]	3740	1		T52	14		T64	21		T217	25
duration[33]	3446	1		T4	1		T5	1		T31	1
duration[34]	4399	1		T4	2		T5	1		T31	3
duration[35]	1906	1		T5	1		T31	1		T64	2
duration[36]	1741	1		T5	3		T19	31		T31	2
duration[37]	1474	1		T5	1		T31	3		T64	1
duration[38]	734	1		T64	1		T217	18		T301	1
duration[39]	2177	1		T217	31		T301	1		T157	1
duration[40]	1425	1		T5	1		T21	1		T25	1
duration[41]	925	1		T31	188		T217	12		T418	1
duration[42]	1583	1		T217	27		T301	1		T139	3
duration[43]	1007	1		T31	360		T217	26		T301	1
duration[44]	327	1		T4	1		T217	19		T418	1
duration[45]	544	1		T217	20		T301	1		T418	2
duration[46]	3408	1		T5	2		T31	769		T32	129
duration[47]	261	1		T5	1		T64	3		T217	17
duration[48]	3002	1		T5	1		T32	265		T217	9
duration[49]	319	1		T64	10		T217	11		T301	1
duration[50]	159609	1		T5	2		T8	3956		T33	4177
duration[51]	303604	1		T8	3794		T33	11441		T156	11745
duration[52]	16993	1		T5	2		T8	772		T33	231
duration[53]	261772	1		T8	753		T33	12525		T50	1
duration[54]	10793	1		T8	5		T33	47		T50	1
duration[55]	8525	1		T6	3		T33	12		T50	4
duration[56]	1457	1		T5	1		T33	12		T156	9
duration[57]	5799	1		T5	1		T33	11		T156	9
duration[58]	3237	1		T49	1		T33	4		T156	11
duration[59]	1277	1		T5	2		T33	7		T156	2
duration[60]	2314	1		T5	1		T33	5		T156	11
duration[61]	2360	1		T4	1		T5	1		T33	4
duration[62]	1370	1		T33	8		T156	1		T64	55
duration[63]	3213	1		T33	3		T156	5		T64	100
duration[64]	3376	1		T5	2		T33	6		T156	158
duration[65]	1690	1		T33	3		T156	2		T64	45
duration[66]	5296	1		T5	1		T33	2		T156	324
duration[67]	1477	1		T5	1		T33	2		T156	2
duration[68]	5462	1		T5	3		T33	2		T156	3
duration[69]	1109	1		T5	1		T156	2		T64	29
duration[70]	1972	1		T5	3		T156	4		T64	14
duration[71]	707	1		T5	1		T33	1		T64	8
duration[72]	2243	1		T5	1		T33	2		T64	9
duration[73]	536	1		T156	1		T64	14		T301	1
duration[74]	686	1		T156	1		T64	10		T301	1
duration[75]	297	1		T33	1		T156	1		T64	6
duration[76]	4136	1		T5	2		T33	150		T156	671
duration[77]	244	1		T5	1		T156	1		T64	8
duration[78]	3551	1		T8	6		T33	993		T156	1
duration[79]	201	1		T5	3		T33	1		T156	3
duration[80]	4097	1		T5	2		T8	21		T33	1
duration[81]	191	1		T33	2		T156	2		T301	2
duration[82]	163	1		T33	5		T156	3		T64	4
duration[83]	128	1		T5	2		T33	3		T156	1
duration[84]	171	1		T33	3		T156	1		T64	2
duration[85]	117	1		T5	1		T33	1		T301	2
duration[86]	117	1		T5	1		T33	4		T156	3
duration[87]	116	1		T156	2		T64	1		T301	3
duration[88]	93	1		T33	5		T156	1		T64	3
duration[89]	96	1		T5	1		T33	4		T156	1
duration[90]	115	1		T5	1		T6	1		T33	3
duration[91]	84	1		T5	1		T33	4		T156	1
duration[92]	97	1		T5	3		T21	1		T33	3
duration[93]	144	1		T7	1		T33	3		T50	1
duration[94]	143	1		T33	4		T25	1		T10	1
duration[95]	91	1		T5	2		T33	2		T301	1
duration[96]	76	1		T5	1		T33	4		T156	1
duration[97]	80	1		T19	1		T33	1		T301	1
duration[98]	69	1		T5	1		T33	4		T156	3
duration[99]	81	1		T5	1		T33	4		T301	1