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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.24 95.73 93.83 98.31 92.52 98.23 96.89 98.15


Total test records in report: 1275
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T154 /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.3258998903 Aug 02 07:42:44 PM PDT 24 Aug 02 07:43:01 PM PDT 24 913483800 ps
T1088 /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3595621458 Aug 02 07:45:20 PM PDT 24 Aug 02 07:46:25 PM PDT 24 10028592000 ps
T1089 /workspace/coverage/default/10.flash_ctrl_connect.3790393810 Aug 02 07:44:55 PM PDT 24 Aug 02 07:45:11 PM PDT 24 25249400 ps
T1090 /workspace/coverage/default/6.flash_ctrl_smoke.2991684070 Aug 02 07:42:58 PM PDT 24 Aug 02 07:43:47 PM PDT 24 17724900 ps
T1091 /workspace/coverage/default/7.flash_ctrl_sec_info_access.2292689581 Aug 02 07:43:44 PM PDT 24 Aug 02 07:45:05 PM PDT 24 9968355500 ps
T1092 /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.906789234 Aug 02 07:38:17 PM PDT 24 Aug 02 07:38:40 PM PDT 24 30554100 ps
T1093 /workspace/coverage/default/1.flash_ctrl_error_mp.320209111 Aug 02 07:39:14 PM PDT 24 Aug 02 08:14:49 PM PDT 24 10625314700 ps
T1094 /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.2295472961 Aug 02 07:37:50 PM PDT 24 Aug 02 07:39:32 PM PDT 24 80238000 ps
T1095 /workspace/coverage/default/7.flash_ctrl_rw_derr.2580657563 Aug 02 07:43:31 PM PDT 24 Aug 02 07:46:17 PM PDT 24 2623491300 ps
T1096 /workspace/coverage/default/5.flash_ctrl_fetch_code.650951091 Aug 02 07:42:44 PM PDT 24 Aug 02 07:43:08 PM PDT 24 144999700 ps
T1097 /workspace/coverage/default/0.flash_ctrl_sw_op.3565444602 Aug 02 07:37:50 PM PDT 24 Aug 02 07:38:17 PM PDT 24 20530700 ps
T1098 /workspace/coverage/default/26.flash_ctrl_otp_reset.4205953099 Aug 02 07:48:19 PM PDT 24 Aug 02 07:50:11 PM PDT 24 147515600 ps
T320 /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.3259614393 Aug 02 07:40:46 PM PDT 24 Aug 02 07:44:27 PM PDT 24 10691310800 ps
T1099 /workspace/coverage/default/6.flash_ctrl_fetch_code.3445932732 Aug 02 07:43:03 PM PDT 24 Aug 02 07:43:28 PM PDT 24 303974100 ps
T1100 /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.1448868929 Aug 02 07:48:30 PM PDT 24 Aug 02 07:49:32 PM PDT 24 6724554500 ps
T1101 /workspace/coverage/default/18.flash_ctrl_smoke.1694507596 Aug 02 07:47:01 PM PDT 24 Aug 02 07:48:42 PM PDT 24 25217000 ps
T1102 /workspace/coverage/default/26.flash_ctrl_sec_info_access.3593055753 Aug 02 07:48:32 PM PDT 24 Aug 02 07:49:42 PM PDT 24 27017949200 ps
T1103 /workspace/coverage/default/0.flash_ctrl_fs_sup.4183905893 Aug 02 07:38:43 PM PDT 24 Aug 02 07:39:27 PM PDT 24 712101500 ps
T1104 /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.4045025012 Aug 02 07:41:50 PM PDT 24 Aug 02 07:55:58 PM PDT 24 50131490400 ps
T1105 /workspace/coverage/default/8.flash_ctrl_ro_serr.10101263 Aug 02 07:44:05 PM PDT 24 Aug 02 07:46:27 PM PDT 24 559746300 ps
T1106 /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.3243588402 Aug 02 07:49:14 PM PDT 24 Aug 02 07:50:31 PM PDT 24 3824963200 ps
T1107 /workspace/coverage/default/3.flash_ctrl_serr_counter.864377536 Aug 02 07:41:11 PM PDT 24 Aug 02 07:42:44 PM PDT 24 14133760200 ps
T409 /workspace/coverage/default/18.flash_ctrl_rw.3329677844 Aug 02 07:47:04 PM PDT 24 Aug 02 07:56:39 PM PDT 24 19114201700 ps
T1108 /workspace/coverage/default/5.flash_ctrl_wo.644716724 Aug 02 07:42:59 PM PDT 24 Aug 02 07:45:47 PM PDT 24 3929312900 ps
T15 /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.765648611 Aug 02 07:41:28 PM PDT 24 Aug 02 07:41:42 PM PDT 24 15312600 ps
T1109 /workspace/coverage/default/3.flash_ctrl_rw_serr.12337345 Aug 02 07:41:12 PM PDT 24 Aug 02 07:44:33 PM PDT 24 11228333800 ps
T1110 /workspace/coverage/default/45.flash_ctrl_disable.2135765473 Aug 02 07:50:18 PM PDT 24 Aug 02 07:50:39 PM PDT 24 12265400 ps
T1111 /workspace/coverage/default/4.flash_ctrl_invalid_op.325161 Aug 02 07:41:49 PM PDT 24 Aug 02 07:43:11 PM PDT 24 1189061800 ps
T1112 /workspace/coverage/default/32.flash_ctrl_connect.1143499533 Aug 02 07:49:12 PM PDT 24 Aug 02 07:49:28 PM PDT 24 46862400 ps
T1113 /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.3481015158 Aug 02 07:42:02 PM PDT 24 Aug 02 07:42:25 PM PDT 24 24390500 ps
T1114 /workspace/coverage/default/19.flash_ctrl_mp_regions.2202944975 Aug 02 07:47:22 PM PDT 24 Aug 02 07:50:16 PM PDT 24 8007087100 ps
T1115 /workspace/coverage/default/45.flash_ctrl_connect.1789404324 Aug 02 07:50:16 PM PDT 24 Aug 02 07:50:32 PM PDT 24 105072200 ps
T1116 /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.72874786 Aug 02 07:39:58 PM PDT 24 Aug 02 07:42:19 PM PDT 24 4258340300 ps
T1117 /workspace/coverage/default/14.flash_ctrl_rw.1939902701 Aug 02 07:45:56 PM PDT 24 Aug 02 07:55:31 PM PDT 24 3888507100 ps
T203 /workspace/coverage/default/8.flash_ctrl_rw_derr.1843636820 Aug 02 07:44:07 PM PDT 24 Aug 02 07:49:04 PM PDT 24 26261602700 ps
T201 /workspace/coverage/default/9.flash_ctrl_ro_derr.1970502473 Aug 02 07:44:26 PM PDT 24 Aug 02 07:46:56 PM PDT 24 773233100 ps
T1118 /workspace/coverage/default/0.flash_ctrl_wo.1337767401 Aug 02 07:38:18 PM PDT 24 Aug 02 07:41:32 PM PDT 24 2197532700 ps
T214 /workspace/coverage/default/4.flash_ctrl_rw_derr.3823652474 Aug 02 07:42:01 PM PDT 24 Aug 02 07:45:49 PM PDT 24 1633764900 ps
T1119 /workspace/coverage/default/18.flash_ctrl_prog_reset.479104453 Aug 02 07:47:18 PM PDT 24 Aug 02 07:47:32 PM PDT 24 81702600 ps
T1120 /workspace/coverage/default/4.flash_ctrl_intr_rd.3759986557 Aug 02 07:42:16 PM PDT 24 Aug 02 07:45:53 PM PDT 24 3489134600 ps
T1121 /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3521385159 Aug 02 07:44:14 PM PDT 24 Aug 02 07:44:28 PM PDT 24 25710400 ps
T1122 /workspace/coverage/default/4.flash_ctrl_intr_wr.1039650905 Aug 02 07:42:15 PM PDT 24 Aug 02 07:43:25 PM PDT 24 4468677500 ps
T1123 /workspace/coverage/default/0.flash_ctrl_erase_suspend.1780545600 Aug 02 07:38:02 PM PDT 24 Aug 02 07:44:40 PM PDT 24 8500737800 ps
T1124 /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.1639380281 Aug 02 07:39:05 PM PDT 24 Aug 02 07:53:15 PM PDT 24 50131119200 ps
T1125 /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1755027456 Aug 02 07:39:48 PM PDT 24 Aug 02 07:41:09 PM PDT 24 10019445900 ps
T1126 /workspace/coverage/default/79.flash_ctrl_connect.762914645 Aug 02 07:51:09 PM PDT 24 Aug 02 07:51:22 PM PDT 24 25775400 ps
T1127 /workspace/coverage/default/17.flash_ctrl_prog_reset.630816723 Aug 02 07:47:04 PM PDT 24 Aug 02 07:47:18 PM PDT 24 24946900 ps
T1128 /workspace/coverage/default/11.flash_ctrl_invalid_op.1117111208 Aug 02 07:45:07 PM PDT 24 Aug 02 07:46:14 PM PDT 24 10136589100 ps
T1129 /workspace/coverage/default/39.flash_ctrl_intr_rd.229104666 Aug 02 07:49:44 PM PDT 24 Aug 02 07:53:09 PM PDT 24 1568126300 ps
T1130 /workspace/coverage/default/0.flash_ctrl_rw_serr.2729880982 Aug 02 07:38:17 PM PDT 24 Aug 02 07:41:54 PM PDT 24 2815653000 ps
T1131 /workspace/coverage/default/9.flash_ctrl_phy_arb.2775412799 Aug 02 07:44:14 PM PDT 24 Aug 02 07:46:51 PM PDT 24 169908700 ps
T1132 /workspace/coverage/default/1.flash_ctrl_ro_derr.348891601 Aug 02 07:39:26 PM PDT 24 Aug 02 07:41:47 PM PDT 24 1333579500 ps
T1133 /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1803935664 Aug 02 07:43:12 PM PDT 24 Aug 02 07:43:53 PM PDT 24 10098183900 ps
T1134 /workspace/coverage/default/79.flash_ctrl_otp_reset.3867623621 Aug 02 07:51:06 PM PDT 24 Aug 02 07:52:56 PM PDT 24 520635100 ps
T1135 /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1192003401 Aug 02 07:49:35 PM PDT 24 Aug 02 07:52:13 PM PDT 24 22441460300 ps
T1136 /workspace/coverage/default/41.flash_ctrl_sec_info_access.2151648015 Aug 02 07:50:09 PM PDT 24 Aug 02 07:51:13 PM PDT 24 506411500 ps
T1137 /workspace/coverage/default/15.flash_ctrl_phy_arb.1438439509 Aug 02 07:46:07 PM PDT 24 Aug 02 07:50:01 PM PDT 24 105094200 ps
T1138 /workspace/coverage/default/7.flash_ctrl_ro.1550077379 Aug 02 07:43:40 PM PDT 24 Aug 02 07:45:49 PM PDT 24 499243400 ps
T1139 /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3899297237 Aug 02 07:44:34 PM PDT 24 Aug 02 07:47:06 PM PDT 24 11710151800 ps
T1140 /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.547745963 Aug 02 07:49:01 PM PDT 24 Aug 02 07:54:00 PM PDT 24 51083798800 ps
T253 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.977218590 Aug 02 07:17:49 PM PDT 24 Aug 02 07:18:03 PM PDT 24 15756400 ps
T69 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2903184463 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:06 PM PDT 24 44849700 ps
T254 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1618932240 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:02 PM PDT 24 81209100 ps
T107 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3893310792 Aug 02 07:19:52 PM PDT 24 Aug 02 07:20:08 PM PDT 24 35653500 ps
T233 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2928222590 Aug 02 07:16:55 PM PDT 24 Aug 02 07:17:09 PM PDT 24 16639400 ps
T70 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.760825823 Aug 02 07:16:08 PM PDT 24 Aug 02 07:17:14 PM PDT 24 11448580500 ps
T1141 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1790215374 Aug 02 07:16:05 PM PDT 24 Aug 02 07:16:19 PM PDT 24 164984300 ps
T71 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1164482927 Aug 02 07:16:18 PM PDT 24 Aug 02 07:23:49 PM PDT 24 1460187500 ps
T108 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1988984055 Aug 02 07:16:57 PM PDT 24 Aug 02 07:17:14 PM PDT 24 111462000 ps
T109 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.469045603 Aug 02 07:19:50 PM PDT 24 Aug 02 07:34:54 PM PDT 24 792226800 ps
T238 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.198141692 Aug 02 07:17:11 PM PDT 24 Aug 02 07:17:31 PM PDT 24 219243700 ps
T255 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3981935584 Aug 02 07:17:11 PM PDT 24 Aug 02 07:17:25 PM PDT 24 29950700 ps
T1142 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3137297145 Aug 02 07:17:48 PM PDT 24 Aug 02 07:18:03 PM PDT 24 12551200 ps
T239 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1510367361 Aug 02 07:19:48 PM PDT 24 Aug 02 07:20:09 PM PDT 24 426442000 ps
T1143 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.527831980 Aug 02 07:19:46 PM PDT 24 Aug 02 07:20:02 PM PDT 24 21237600 ps
T234 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.585535855 Aug 02 07:16:18 PM PDT 24 Aug 02 07:16:31 PM PDT 24 18168100 ps
T240 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2398231148 Aug 02 07:17:11 PM PDT 24 Aug 02 07:17:28 PM PDT 24 104474500 ps
T215 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3219963475 Aug 02 07:17:12 PM PDT 24 Aug 02 07:17:28 PM PDT 24 48829200 ps
T1144 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2182916846 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:02 PM PDT 24 25362400 ps
T1145 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3125741471 Aug 02 07:17:47 PM PDT 24 Aug 02 07:18:03 PM PDT 24 36812600 ps
T216 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3558834008 Aug 02 07:17:11 PM PDT 24 Aug 02 07:17:27 PM PDT 24 77733100 ps
T327 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1899553446 Aug 02 07:16:22 PM PDT 24 Aug 02 07:16:36 PM PDT 24 113916700 ps
T257 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1969377780 Aug 02 07:16:57 PM PDT 24 Aug 02 07:17:42 PM PDT 24 84426600 ps
T241 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3275935007 Aug 02 07:17:37 PM PDT 24 Aug 02 07:18:12 PM PDT 24 834185000 ps
T328 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1433774144 Aug 02 07:19:45 PM PDT 24 Aug 02 07:19:59 PM PDT 24 154119600 ps
T329 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3879495704 Aug 02 07:19:57 PM PDT 24 Aug 02 07:20:10 PM PDT 24 35108200 ps
T224 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2986513348 Aug 02 07:19:45 PM PDT 24 Aug 02 07:20:02 PM PDT 24 40211200 ps
T258 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3447385545 Aug 02 07:16:08 PM PDT 24 Aug 02 07:16:46 PM PDT 24 27124500 ps
T423 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3886262190 Aug 02 07:17:12 PM PDT 24 Aug 02 07:17:57 PM PDT 24 87646000 ps
T242 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.814867318 Aug 02 07:17:26 PM PDT 24 Aug 02 07:17:47 PM PDT 24 156093400 ps
T330 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.31475727 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:03 PM PDT 24 46704200 ps
T225 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.542316544 Aug 02 07:16:58 PM PDT 24 Aug 02 07:17:15 PM PDT 24 369512400 ps
T1146 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3438122577 Aug 02 07:19:52 PM PDT 24 Aug 02 07:20:06 PM PDT 24 21426900 ps
T1147 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1806389707 Aug 02 07:17:46 PM PDT 24 Aug 02 07:17:59 PM PDT 24 12184800 ps
T226 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3906107568 Aug 02 07:19:46 PM PDT 24 Aug 02 07:32:24 PM PDT 24 1578963100 ps
T227 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2673956232 Aug 02 07:19:49 PM PDT 24 Aug 02 07:34:54 PM PDT 24 4322557000 ps
T228 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2522121645 Aug 02 07:16:06 PM PDT 24 Aug 02 07:16:23 PM PDT 24 78653300 ps
T291 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3971309039 Aug 02 07:17:11 PM PDT 24 Aug 02 07:18:12 PM PDT 24 2999678500 ps
T347 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1974877678 Aug 02 07:19:47 PM PDT 24 Aug 02 07:20:00 PM PDT 24 49292200 ps
T1148 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3442560958 Aug 02 07:17:12 PM PDT 24 Aug 02 07:17:25 PM PDT 24 40573300 ps
T331 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1078366959 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:14 PM PDT 24 52348000 ps
T243 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.677440796 Aug 02 07:17:50 PM PDT 24 Aug 02 07:18:07 PM PDT 24 34662100 ps
T1149 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2606901352 Aug 02 07:17:25 PM PDT 24 Aug 02 07:17:39 PM PDT 24 14562100 ps
T229 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.197333381 Aug 02 07:17:48 PM PDT 24 Aug 02 07:32:36 PM PDT 24 1326002300 ps
T1150 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1684991485 Aug 02 07:17:26 PM PDT 24 Aug 02 07:17:42 PM PDT 24 19383300 ps
T332 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2942486932 Aug 02 07:19:50 PM PDT 24 Aug 02 07:20:03 PM PDT 24 27857400 ps
T292 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3057163651 Aug 02 07:16:06 PM PDT 24 Aug 02 07:17:14 PM PDT 24 4798239400 ps
T1151 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.431064970 Aug 02 07:19:46 PM PDT 24 Aug 02 07:20:01 PM PDT 24 44785600 ps
T1152 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.203309058 Aug 02 07:17:36 PM PDT 24 Aug 02 07:17:50 PM PDT 24 114316300 ps
T230 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.222554101 Aug 02 07:19:47 PM PDT 24 Aug 02 07:20:05 PM PDT 24 138810700 ps
T1153 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2651886147 Aug 02 07:19:46 PM PDT 24 Aug 02 07:20:00 PM PDT 24 26617100 ps
T349 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2249883630 Aug 02 07:19:46 PM PDT 24 Aug 02 07:27:18 PM PDT 24 1790977700 ps
T231 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.7685196 Aug 02 07:17:34 PM PDT 24 Aug 02 07:17:50 PM PDT 24 569693300 ps
T1154 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1748209825 Aug 02 07:19:46 PM PDT 24 Aug 02 07:20:02 PM PDT 24 31073500 ps
T244 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3328319398 Aug 02 07:17:36 PM PDT 24 Aug 02 07:17:53 PM PDT 24 114074700 ps
T293 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3374004042 Aug 02 07:16:43 PM PDT 24 Aug 02 07:16:59 PM PDT 24 670833200 ps
T294 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.18136021 Aug 02 07:17:12 PM PDT 24 Aug 02 07:17:32 PM PDT 24 734697100 ps
T232 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.176321702 Aug 02 07:17:11 PM PDT 24 Aug 02 07:32:03 PM PDT 24 1168911600 ps
T1155 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4157446890 Aug 02 07:17:26 PM PDT 24 Aug 02 07:17:39 PM PDT 24 54165500 ps
T1156 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3390509100 Aug 02 07:19:47 PM PDT 24 Aug 02 07:20:06 PM PDT 24 421713500 ps
T264 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.225537217 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:04 PM PDT 24 58194500 ps
T1157 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.4020011187 Aug 02 07:19:47 PM PDT 24 Aug 02 07:20:01 PM PDT 24 45350400 ps
T1158 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.878427449 Aug 02 07:16:41 PM PDT 24 Aug 02 07:17:19 PM PDT 24 81348500 ps
T1159 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3977542065 Aug 02 07:17:48 PM PDT 24 Aug 02 07:18:02 PM PDT 24 26088400 ps
T1160 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.4154054929 Aug 02 07:17:25 PM PDT 24 Aug 02 07:17:43 PM PDT 24 230582000 ps
T1161 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1107975597 Aug 02 07:19:56 PM PDT 24 Aug 02 07:20:10 PM PDT 24 16114300 ps
T1162 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3129822664 Aug 02 07:19:47 PM PDT 24 Aug 02 07:20:00 PM PDT 24 16421300 ps
T269 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.334295443 Aug 02 07:19:48 PM PDT 24 Aug 02 07:20:03 PM PDT 24 86624500 ps
T1163 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2532799374 Aug 02 07:17:48 PM PDT 24 Aug 02 07:18:04 PM PDT 24 12737200 ps
T250 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.302434620 Aug 02 07:19:46 PM PDT 24 Aug 02 07:20:02 PM PDT 24 35879800 ps
T235 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3364772857 Aug 02 07:16:05 PM PDT 24 Aug 02 07:16:19 PM PDT 24 16682700 ps
T295 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2980473185 Aug 02 07:17:50 PM PDT 24 Aug 02 07:18:24 PM PDT 24 726076300 ps
T1164 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2281640287 Aug 02 07:16:19 PM PDT 24 Aug 02 07:16:36 PM PDT 24 36264800 ps
T1165 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1015439908 Aug 02 07:17:36 PM PDT 24 Aug 02 07:17:51 PM PDT 24 134568300 ps
T1166 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3120872780 Aug 02 07:19:47 PM PDT 24 Aug 02 07:20:00 PM PDT 24 17927100 ps
T268 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3864254455 Aug 02 07:19:52 PM PDT 24 Aug 02 07:20:08 PM PDT 24 133181300 ps
T1167 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2904225775 Aug 02 07:16:59 PM PDT 24 Aug 02 07:17:36 PM PDT 24 1631114000 ps
T1168 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2314569421 Aug 02 07:19:47 PM PDT 24 Aug 02 07:20:03 PM PDT 24 64958300 ps
T296 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.427707100 Aug 02 07:19:50 PM PDT 24 Aug 02 07:20:07 PM PDT 24 163142600 ps
T1169 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.604804988 Aug 02 07:16:58 PM PDT 24 Aug 02 07:17:11 PM PDT 24 14268100 ps
T1170 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3925190340 Aug 02 07:17:48 PM PDT 24 Aug 02 07:18:02 PM PDT 24 86006300 ps
T1171 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3112796719 Aug 02 07:16:45 PM PDT 24 Aug 02 07:17:18 PM PDT 24 855852300 ps
T1172 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1867082829 Aug 02 07:17:24 PM PDT 24 Aug 02 07:17:41 PM PDT 24 91702500 ps
T1173 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.592202406 Aug 02 07:16:21 PM PDT 24 Aug 02 07:16:37 PM PDT 24 49534300 ps
T1174 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.982196766 Aug 02 07:19:50 PM PDT 24 Aug 02 07:20:09 PM PDT 24 231383100 ps
T1175 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1373672329 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:02 PM PDT 24 52671700 ps
T1176 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.336866894 Aug 02 07:17:26 PM PDT 24 Aug 02 07:17:42 PM PDT 24 19008600 ps
T263 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3591989939 Aug 02 07:17:36 PM PDT 24 Aug 02 07:17:52 PM PDT 24 32687300 ps
T1177 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1689615434 Aug 02 07:16:48 PM PDT 24 Aug 02 07:17:02 PM PDT 24 393347200 ps
T248 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.595935115 Aug 02 07:16:05 PM PDT 24 Aug 02 07:16:23 PM PDT 24 192182900 ps
T1178 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2891071213 Aug 02 07:16:45 PM PDT 24 Aug 02 07:17:00 PM PDT 24 119751100 ps
T297 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2331944787 Aug 02 07:17:35 PM PDT 24 Aug 02 07:17:53 PM PDT 24 117105500 ps
T265 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2399354637 Aug 02 07:17:25 PM PDT 24 Aug 02 07:30:08 PM PDT 24 2639282100 ps
T1179 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4178464431 Aug 02 07:16:04 PM PDT 24 Aug 02 07:16:18 PM PDT 24 11945400 ps
T348 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2604149957 Aug 02 07:16:53 PM PDT 24 Aug 02 07:24:28 PM PDT 24 395364400 ps
T354 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1463615564 Aug 02 07:16:44 PM PDT 24 Aug 02 07:24:20 PM PDT 24 1778369000 ps
T1180 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3855678292 Aug 02 07:19:51 PM PDT 24 Aug 02 07:20:08 PM PDT 24 74592000 ps
T1181 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.280083166 Aug 02 07:17:26 PM PDT 24 Aug 02 07:17:44 PM PDT 24 251817400 ps
T1182 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2877448706 Aug 02 07:19:58 PM PDT 24 Aug 02 07:20:11 PM PDT 24 37326700 ps
T256 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4219585630 Aug 02 07:19:50 PM PDT 24 Aug 02 07:20:10 PM PDT 24 178444100 ps
T1183 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.209830300 Aug 02 07:19:46 PM PDT 24 Aug 02 07:19:59 PM PDT 24 24267800 ps
T1184 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4083270916 Aug 02 07:19:48 PM PDT 24 Aug 02 07:20:06 PM PDT 24 55280500 ps
T298 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4121642095 Aug 02 07:19:46 PM PDT 24 Aug 02 07:20:04 PM PDT 24 114224900 ps
T1185 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3709792130 Aug 02 07:19:47 PM PDT 24 Aug 02 07:20:00 PM PDT 24 13118900 ps
T249 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1093403385 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:09 PM PDT 24 54754200 ps
T1186 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2844249198 Aug 02 07:17:25 PM PDT 24 Aug 02 07:17:38 PM PDT 24 19163500 ps
T1187 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1023985588 Aug 02 07:19:54 PM PDT 24 Aug 02 07:20:08 PM PDT 24 16046200 ps
T299 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3364464096 Aug 02 07:17:11 PM PDT 24 Aug 02 07:17:29 PM PDT 24 170857400 ps
T266 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1438440452 Aug 02 07:19:48 PM PDT 24 Aug 02 07:27:27 PM PDT 24 685369400 ps
T267 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2464453762 Aug 02 07:16:06 PM PDT 24 Aug 02 07:30:55 PM PDT 24 1639954200 ps
T353 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.174515808 Aug 02 07:19:48 PM PDT 24 Aug 02 07:32:31 PM PDT 24 1689339300 ps
T1188 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2056572733 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:02 PM PDT 24 20683400 ps
T251 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3197328429 Aug 02 07:17:25 PM PDT 24 Aug 02 07:17:46 PM PDT 24 182634200 ps
T1189 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2311699660 Aug 02 07:17:25 PM PDT 24 Aug 02 07:17:39 PM PDT 24 14856800 ps
T1190 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.365173314 Aug 02 07:16:07 PM PDT 24 Aug 02 07:16:22 PM PDT 24 67153800 ps
T1191 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4228362305 Aug 02 07:16:56 PM PDT 24 Aug 02 07:17:10 PM PDT 24 15493200 ps
T1192 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2621979429 Aug 02 07:17:09 PM PDT 24 Aug 02 07:17:25 PM PDT 24 11855200 ps
T1193 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.183360004 Aug 02 07:19:48 PM PDT 24 Aug 02 07:20:05 PM PDT 24 52683800 ps
T1194 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.903330803 Aug 02 07:16:19 PM PDT 24 Aug 02 07:16:33 PM PDT 24 35288100 ps
T259 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2038513570 Aug 02 07:17:25 PM PDT 24 Aug 02 07:17:45 PM PDT 24 183557800 ps
T1195 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3197549517 Aug 02 07:16:43 PM PDT 24 Aug 02 07:16:56 PM PDT 24 38682600 ps
T1196 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1351208184 Aug 02 07:19:48 PM PDT 24 Aug 02 07:20:01 PM PDT 24 17535000 ps
T1197 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2596828068 Aug 02 07:17:26 PM PDT 24 Aug 02 07:17:44 PM PDT 24 109557200 ps
T271 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1180430948 Aug 02 07:17:09 PM PDT 24 Aug 02 07:24:45 PM PDT 24 423514700 ps
T1198 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2543819129 Aug 02 07:17:11 PM PDT 24 Aug 02 07:17:25 PM PDT 24 75987100 ps
T1199 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1942958924 Aug 02 07:19:59 PM PDT 24 Aug 02 07:20:13 PM PDT 24 51079300 ps
T1200 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3538099550 Aug 02 07:19:58 PM PDT 24 Aug 02 07:20:12 PM PDT 24 34863100 ps
T355 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2634827804 Aug 02 07:19:46 PM PDT 24 Aug 02 07:34:25 PM PDT 24 2731688100 ps
T1201 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3570577220 Aug 02 07:16:05 PM PDT 24 Aug 02 07:16:21 PM PDT 24 164175400 ps
T1202 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.414519351 Aug 02 07:17:26 PM PDT 24 Aug 02 07:17:43 PM PDT 24 94878900 ps
T1203 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2359585968 Aug 02 07:19:54 PM PDT 24 Aug 02 07:20:10 PM PDT 24 74719900 ps
T1204 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1346842349 Aug 02 07:16:06 PM PDT 24 Aug 02 07:16:22 PM PDT 24 12578100 ps
T1205 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3050945951 Aug 02 07:19:50 PM PDT 24 Aug 02 07:20:08 PM PDT 24 38494400 ps
T1206 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2808108542 Aug 02 07:16:55 PM PDT 24 Aug 02 07:24:32 PM PDT 24 544169100 ps
T1207 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.527546972 Aug 02 07:16:21 PM PDT 24 Aug 02 07:16:37 PM PDT 24 38456800 ps
T252 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1677714642 Aug 02 07:16:56 PM PDT 24 Aug 02 07:17:18 PM PDT 24 1144847900 ps
T236 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3877443891 Aug 02 07:16:45 PM PDT 24 Aug 02 07:16:58 PM PDT 24 27024400 ps
T1208 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2663740766 Aug 02 07:16:43 PM PDT 24 Aug 02 07:17:01 PM PDT 24 291321600 ps
T1209 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2424212479 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:04 PM PDT 24 50031700 ps
T1210 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.889171081 Aug 02 07:19:53 PM PDT 24 Aug 02 07:20:10 PM PDT 24 33252100 ps
T351 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3846456819 Aug 02 07:17:23 PM PDT 24 Aug 02 07:25:05 PM PDT 24 1707426800 ps
T1211 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.634577759 Aug 02 07:19:46 PM PDT 24 Aug 02 07:20:03 PM PDT 24 128336500 ps
T300 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3210435847 Aug 02 07:16:58 PM PDT 24 Aug 02 07:17:16 PM PDT 24 64710900 ps
T1212 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.697965481 Aug 02 07:19:54 PM PDT 24 Aug 02 07:20:29 PM PDT 24 159127500 ps
T1213 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.432928718 Aug 02 07:17:53 PM PDT 24 Aug 02 07:18:27 PM PDT 24 71058000 ps
T1214 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.598264643 Aug 02 07:16:18 PM PDT 24 Aug 02 07:17:21 PM PDT 24 2537182300 ps
T1215 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1645877164 Aug 02 07:17:11 PM PDT 24 Aug 02 07:17:24 PM PDT 24 24729500 ps
T1216 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3014433438 Aug 02 07:19:48 PM PDT 24 Aug 02 07:20:01 PM PDT 24 13791800 ps
T1217 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.420765393 Aug 02 07:16:08 PM PDT 24 Aug 02 07:16:25 PM PDT 24 39723100 ps
T1218 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3624016012 Aug 02 07:16:52 PM PDT 24 Aug 02 07:17:06 PM PDT 24 28278200 ps
T1219 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2052422373 Aug 02 07:17:25 PM PDT 24 Aug 02 07:17:41 PM PDT 24 339774400 ps
T1220 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2823422202 Aug 02 07:16:42 PM PDT 24 Aug 02 07:16:55 PM PDT 24 55124600 ps
T1221 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1865592994 Aug 02 07:16:41 PM PDT 24 Aug 02 07:16:57 PM PDT 24 77335600 ps
T1222 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2148408031 Aug 02 07:19:48 PM PDT 24 Aug 02 07:20:01 PM PDT 24 58173000 ps
T1223 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3633259251 Aug 02 07:19:47 PM PDT 24 Aug 02 07:20:01 PM PDT 24 49387100 ps
T1224 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2551689903 Aug 02 07:19:59 PM PDT 24 Aug 02 07:20:12 PM PDT 24 18712600 ps
T350 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2465369283 Aug 02 07:19:51 PM PDT 24 Aug 02 07:34:49 PM PDT 24 1116185700 ps
T261 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3572478152 Aug 02 07:17:50 PM PDT 24 Aug 02 07:18:07 PM PDT 24 36905600 ps
T1225 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.302567115 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:02 PM PDT 24 14929400 ps
T1226 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2908822583 Aug 02 07:19:57 PM PDT 24 Aug 02 07:20:11 PM PDT 24 56383500 ps
T1227 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1656633326 Aug 02 07:19:48 PM PDT 24 Aug 02 07:20:01 PM PDT 24 55279600 ps
T352 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1467019563 Aug 02 07:17:48 PM PDT 24 Aug 02 07:25:17 PM PDT 24 687902400 ps
T272 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1436854733 Aug 02 07:17:35 PM PDT 24 Aug 02 07:32:35 PM PDT 24 668992400 ps
T1228 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1606020435 Aug 02 07:19:46 PM PDT 24 Aug 02 07:19:59 PM PDT 24 13094800 ps
T1229 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1199623743 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:14 PM PDT 24 18330800 ps
T262 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3655418443 Aug 02 07:17:34 PM PDT 24 Aug 02 07:17:55 PM PDT 24 411620200 ps
T1230 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2852681277 Aug 02 07:17:11 PM PDT 24 Aug 02 07:17:26 PM PDT 24 20554300 ps
T1231 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.45099249 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:02 PM PDT 24 45734600 ps
T1232 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2370222110 Aug 02 07:19:47 PM PDT 24 Aug 02 07:20:23 PM PDT 24 209141700 ps
T1233 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2144376012 Aug 02 07:19:45 PM PDT 24 Aug 02 07:20:01 PM PDT 24 23010200 ps
T1234 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.840433706 Aug 02 07:19:50 PM PDT 24 Aug 02 07:20:04 PM PDT 24 18212200 ps
T1235 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1006855440 Aug 02 07:19:48 PM PDT 24 Aug 02 07:20:05 PM PDT 24 250542700 ps
T1236 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3387445581 Aug 02 07:16:41 PM PDT 24 Aug 02 07:16:54 PM PDT 24 55269700 ps
T1237 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3420785145 Aug 02 07:17:09 PM PDT 24 Aug 02 07:17:25 PM PDT 24 17954600 ps
T1238 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2452103680 Aug 02 07:19:46 PM PDT 24 Aug 02 07:20:05 PM PDT 24 56850700 ps
T1239 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1441098889 Aug 02 07:16:20 PM PDT 24 Aug 02 07:17:22 PM PDT 24 1315750400 ps
T1240 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1910404063 Aug 02 07:16:04 PM PDT 24 Aug 02 07:16:18 PM PDT 24 59183800 ps
T1241 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.4185176225 Aug 02 07:20:02 PM PDT 24 Aug 02 07:20:15 PM PDT 24 15711500 ps
T1242 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1681218953 Aug 02 07:19:45 PM PDT 24 Aug 02 07:19:59 PM PDT 24 63860800 ps
T1243 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2972109418 Aug 02 07:16:52 PM PDT 24 Aug 02 07:17:28 PM PDT 24 330700200 ps
T1244 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.130342853 Aug 02 07:17:11 PM PDT 24 Aug 02 07:17:26 PM PDT 24 71661800 ps
T1245 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1180449542 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:13 PM PDT 24 20092100 ps
T1246 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2127731351 Aug 02 07:19:51 PM PDT 24 Aug 02 07:20:07 PM PDT 24 114030600 ps
T1247 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3043672435 Aug 02 07:19:59 PM PDT 24 Aug 02 07:20:13 PM PDT 24 18664300 ps
T1248 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.435663588 Aug 02 07:19:49 PM PDT 24 Aug 02 07:20:03 PM PDT 24 31184800 ps
T1249 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.847430198 Aug 02 07:17:11 PM PDT 24 Aug 02 07:17:58 PM PDT 24 4641763700 ps
T1250 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.674541676 Aug 02 07:19:56 PM PDT 24 Aug 02 07:20:09 PM PDT 24 75275400 ps
T1251 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.378220265 Aug 02 07:17:26 PM PDT 24 Aug 02 07:17:45 PM PDT 24 323438000 ps
T1252 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.642276279 Aug 02 07:19:48 PM PDT 24 Aug 02 07:20:02 PM PDT 24 13177900 ps
T1253 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1658117239 Aug 02 07:16:57 PM PDT 24 Aug 02 07:17:14 PM PDT 24 91527100 ps
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