Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	325980	1		T1	2		T2	3365		T3	2
all_values[1]	325980	1		T1	2		T2	3365		T3	2
all_values[2]	325980	1		T1	2		T2	3365		T3	2
all_values[3]	325980	1		T1	2		T2	3365		T3	2
all_values[4]	325980	1		T1	2		T2	3365		T3	2
all_values[5]	325980	1		T1	2		T2	3365		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	658453	1		T1	12		T2	6734		T3	12
auto[1]	1297427	1		T2	13456		T6	12352		T42	34936

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	958543	1		T1	7		T2	10096		T3	7
auto[1]	997337	1		T1	5		T2	10094		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	325818	1		T1	2		T2	3365		T3	2
all_values[0]	auto[1]	auto[1]	162	1		T257	4		T258	3		T259	4
all_values[1]	auto[0]	auto[1]	325830	1		T1	2		T2	3365		T3	2
all_values[1]	auto[1]	auto[1]	150	1		T258	1		T259	2		T320	7
all_values[2]	auto[0]	auto[0]	1652	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	53	1		T257	1		T258	1		T320	1
all_values[2]	auto[1]	auto[0]	324207	1		T2	3364		T6	3088		T42	8734
all_values[2]	auto[1]	auto[1]	68	1		T259	4		T320	1		T321	2
all_values[3]	auto[0]	auto[0]	1641	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	59	1		T257	1		T258	1		T259	3
all_values[3]	auto[1]	auto[0]	80450	1		T2	1682		T6	1544		T42	250
all_values[3]	auto[1]	auto[1]	243830	1		T2	1682		T6	1544		T42	8484
all_values[4]	auto[0]	auto[0]	1153	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	549	1		T1	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	223615	1		T2	1682		T6	1544		T42	7043
all_values[4]	auto[1]	auto[1]	100663	1		T2	1682		T6	1544		T42	1691
all_values[5]	auto[0]	auto[0]	1614	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	84	1		T16	1		T43	1		T44	1
all_values[5]	auto[1]	auto[0]	324211	1		T2	3364		T6	3088		T42	8734
all_values[5]	auto[1]	auto[1]	71	1		T257	1		T258	1		T259	2