Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	2	14	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	2	14	87.50	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	238274	1		T1	28		T2	777		T3	422
auto[FlashEraseBank]	266945	1		T1	38		T2	905		T3	525

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	249328	1		T2	1682		T3	380		T4	13
auto[FlashOpProgram]	236015	1		T1	66		T3	567		T4	288
auto[FlashOpErase]	15876	1		T4	8		T17	100		T5	1
auto[FlashOpInvalid]	4000	1		T17	200		T142	200		T278	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	249328	1		T2	1682		T3	380		T4	13
op[FlashOpProgram]	236015	1		T1	66		T3	567		T4	288
op[FlashOpErase]	15876	1		T4	8		T17	100		T5	1
read_erase_read	537	1		T4	1		T25	1		T38	2
read_prog_read	901	1		T3	5		T5	1		T43	6

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	364931	1		T1	66		T2	1682		T3	738
auto[FlashPartInfo]	136430	1		T3	199		T4	309		T16	198
auto[FlashPartInfo1]	992	1		T43	1		T53	32		T22	33
auto[FlashPartInfo2]	2866	1		T3	10		T16	10		T43	6

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpErase] , auto[FlashOpInvalid]]	--	--	2

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	179264	1		T2	1682		T3	239		T6	1544
auto[FlashPartData]	auto[FlashOpProgram]	178138	1		T1	66		T3	499		T17	98
auto[FlashPartData]	auto[FlashOpErase]	3597	1		T17	98		T5	1		T25	9
auto[FlashPartData]	auto[FlashOpInvalid]	3932	1		T17	196		T142	190		T278	198
auto[FlashPartInfo]	auto[FlashOpRead]	67389	1		T3	134		T4	13		T16	198
auto[FlashPartInfo]	auto[FlashOpProgram]	56715	1		T3	65		T4	288		T17	2
auto[FlashPartInfo]	auto[FlashOpErase]	12260	1		T4	8		T17	2		T27	124
auto[FlashPartInfo]	auto[FlashOpInvalid]	66	1		T17	4		T142	10		T278	2
auto[FlashPartInfo1]	auto[FlashOpRead]	831	1		T43	1		T53	32		T22	33
auto[FlashPartInfo1]	auto[FlashOpProgram]	161	1		T146	1		T332	32		T333	32
auto[FlashPartInfo2]	auto[FlashOpRead]	1844	1		T3	7		T16	10		T43	6
auto[FlashPartInfo2]	auto[FlashOpProgram]	1001	1		T3	3		T32	1		T33	1
auto[FlashPartInfo2]	auto[FlashOpErase]	19	1		T148	1		T85	1		T206	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	2	1		T85	2		-	-		-	-