Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31313	1		T17	400		T27	244		T25	10
auto[1]	23	1		T31	1		T182	1		T334	2
auto[2]	64	1		T32	1		T46	1		T312	1
auto[3]	245	1		T32	1		T33	1		T101	9

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7908	1		T17	100		T27	61		T33	1
evic_idx[1]	7924	1		T17	100		T32	2		T27	61
evic_idx[2]	7908	1		T17	100		T31	1		T27	61
evic_idx[3]	7905	1		T17	100		T27	61		T25	3

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30746	1		T17	400		T27	244		T25	1
evic_op[2]	365	1		T31	1		T32	2		T33	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[2]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7628	1		T17	100		T27	61		T28	1
evic_idx[0]	evic_op[1]	auto[1]	4	1		T335	2		T336	1		T337	1
evic_idx[0]	evic_op[1]	auto[2]	5	1		T338	1		T152	2		T339	2
evic_idx[0]	evic_op[1]	auto[3]	49	1		T101	2		T312	3		T206	7
evic_idx[0]	evic_op[2]	auto[0]	74	1		T25	1		T203	10		T215	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T182	1		T340	1		T341	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T342	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	9	1		T33	1		T143	1		T197	1
evic_idx[1]	evic_op[1]	auto[0]	7625	1		T17	100		T27	61		T28	1
evic_idx[1]	evic_op[1]	auto[1]	4	1		T335	3		T336	1		-	-
evic_idx[1]	evic_op[1]	auto[2]	9	1		T338	1		T152	1		T343	1
evic_idx[1]	evic_op[1]	auto[3]	56	1		T101	1		T312	3		T206	6
evic_idx[1]	evic_op[2]	auto[0]	76	1		T203	10		T344	1		T210	4
evic_idx[1]	evic_op[2]	auto[1]	1	1		T334	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	7	1		T32	1		T345	1		T346	1
evic_idx[1]	evic_op[2]	auto[3]	12	1		T32	1		T46	1		T183	1
evic_idx[2]	evic_op[1]	auto[0]	7626	1		T17	100		T27	61		T28	1
evic_idx[2]	evic_op[1]	auto[1]	2	1		T335	1		T343	1		-	-
evic_idx[2]	evic_op[1]	auto[2]	7	1		T338	1		T152	1		T347	1
evic_idx[2]	evic_op[1]	auto[3]	51	1		T101	3		T312	4		T206	4
evic_idx[2]	evic_op[2]	auto[0]	76	1		T203	10		T210	4		T348	4
evic_idx[2]	evic_op[2]	auto[1]	2	1		T31	1		T334	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	10	1		T349	1		T350	1		T351	1
evic_idx[3]	evic_op[1]	auto[0]	7624	1		T17	100		T27	61		T25	1
evic_idx[3]	evic_op[1]	auto[1]	3	1		T335	2		T337	1		-	-
evic_idx[3]	evic_op[1]	auto[2]	6	1		T312	1		T338	1		T152	1
evic_idx[3]	evic_op[1]	auto[3]	47	1		T101	3		T312	2		T206	4
evic_idx[3]	evic_op[2]	auto[0]	74	1		T203	10		T210	4		T348	4
evic_idx[3]	evic_op[2]	auto[1]	3	1		T352	1		T353	1		T354	1
evic_idx[3]	evic_op[2]	auto[2]	5	1		T46	1		T355	2		T354	1
evic_idx[3]	evic_op[2]	auto[3]	11	1		T283	1		T125	1		T127	1