Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	22318	1		T22	2266		T140	1801		T325	1588
rd_lvl[2]	35817	1		T22	946		T24	12012		T140	1531
rd_lvl[3]	16871	1		T42	1282		T22	452		T24	514
rd_lvl[4]	50185	1		T42	5963		T22	197		T140	536
rd_lvl[5]	21855	1		T42	1050		T22	91		T23	465
rd_lvl[6]	25438	1		T22	30		T23	378		T140	92
rd_lvl[7]	6114	1		T22	21		T23	52		T140	206
rd_lvl[8]	4693	1		T22	19		T23	190		T140	224
rd_lvl[9]	4686	1		T22	17		T140	295		T326	90
rd_lvl[10]	5138	1		T2	1455		T22	3		T140	118
rd_lvl[11]	6119	1		T2	227		T22	39		T23	190
rd_lvl[12]	1303	1		T41	162		T327	17		T328	6
rd_lvl[13]	2609	1		T6	480		T205	479		T199	35
rd_lvl[14]	8286	1		T6	1064		T22	39		T69	60
rd_lvl[15]	3749	1		T69	7		T39	261		T40	1