Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	325980	1		T1	2		T2	3365		T3	2
all_pins[1]	325980	1		T1	2		T2	3365		T3	2
all_pins[2]	325980	1		T1	2		T2	3365		T3	2
all_pins[3]	325980	1		T1	2		T2	3365		T3	2
all_pins[4]	325980	1		T1	2		T2	3365		T3	2
all_pins[5]	325980	1		T1	2		T2	3365		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1618709	1		T1	12		T2	16826		T3	12
values[0x1]	337171	1		T2	3364		T6	3088		T42	10038
transitions[0x0=>0x1]	301227	1		T2	3364		T6	3088		T42	8566
transitions[0x1=>0x0]	301209	1		T2	3364		T6	3088		T42	8566

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	325818	1		T1	2		T2	3365		T3	2
all_pins[0]	values[0x1]	162	1		T257	4		T258	3		T259	4
all_pins[0]	transitions[0x0=>0x1]	96	1		T257	4		T258	3		T259	2
all_pins[0]	transitions[0x1=>0x0]	84	1		T258	1		T320	5		T322	2
all_pins[1]	values[0x0]	325830	1		T1	2		T2	3365		T3	2
all_pins[1]	values[0x1]	150	1		T258	1		T259	2		T320	7
all_pins[1]	transitions[0x0=>0x1]	115	1		T258	1		T259	1		T320	6
all_pins[1]	transitions[0x1=>0x0]	4465	1		T39	316		T356	1184		T357	1173
all_pins[2]	values[0x0]	321480	1		T1	2		T2	3365		T3	2
all_pins[2]	values[0x1]	4500	1		T39	316		T356	1184		T357	1173
all_pins[2]	transitions[0x0=>0x1]	44	1		T259	3		T320	1		T321	1
all_pins[2]	transitions[0x1=>0x0]	215837	1		T2	1682		T6	1544		T42	8295
all_pins[3]	values[0x0]	105687	1		T1	2		T2	1683		T3	2
all_pins[3]	values[0x1]	220293	1		T2	1682		T6	1544		T42	8295
all_pins[3]	transitions[0x0=>0x1]	188956	1		T2	1682		T6	1544		T42	6823
all_pins[3]	transitions[0x1=>0x0]	80658	1		T2	1682		T6	1544		T42	271
all_pins[4]	values[0x0]	213985	1		T1	2		T2	1683		T3	2
all_pins[4]	values[0x1]	111995	1		T2	1682		T6	1544		T42	1743
all_pins[4]	transitions[0x0=>0x1]	111983	1		T2	1682		T6	1544		T42	1743
all_pins[4]	transitions[0x1=>0x0]	59	1		T257	1		T258	1		T259	1
all_pins[5]	values[0x0]	325909	1		T1	2		T2	3365		T3	2
all_pins[5]	values[0x1]	71	1		T257	1		T258	1		T259	2
all_pins[5]	transitions[0x0=>0x1]	33	1		T257	1		T358	2		T323	1
all_pins[5]	transitions[0x1=>0x0]	106	1		T257	3		T258	2		T259	3