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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.94 95.25 93.96 98.31 91.84 97.21 96.89 98.12


Total test records in report: 1273
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T1095 /workspace/coverage/default/1.flash_ctrl_oversize_error.2445976438 Aug 03 06:22:32 PM PDT 24 Aug 03 06:26:13 PM PDT 24 6530378300 ps
T1096 /workspace/coverage/default/1.flash_ctrl_config_regwen.2401141569 Aug 03 06:22:48 PM PDT 24 Aug 03 06:23:02 PM PDT 24 60294400 ps
T1097 /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.1313205893 Aug 03 06:32:19 PM PDT 24 Aug 03 06:34:28 PM PDT 24 11276945600 ps
T1098 /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.3514647695 Aug 03 06:30:45 PM PDT 24 Aug 03 06:31:51 PM PDT 24 2940617800 ps
T1099 /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1616922802 Aug 03 06:21:06 PM PDT 24 Aug 03 06:34:48 PM PDT 24 40125512800 ps
T1100 /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3421784297 Aug 03 06:25:39 PM PDT 24 Aug 03 06:34:32 PM PDT 24 121541546900 ps
T61 /workspace/coverage/default/2.flash_ctrl_sec_cm.3234947969 Aug 03 06:23:40 PM PDT 24 Aug 03 07:42:31 PM PDT 24 4543676300 ps
T1101 /workspace/coverage/default/5.flash_ctrl_error_mp.2767258421 Aug 03 06:25:28 PM PDT 24 Aug 03 07:03:41 PM PDT 24 6046108600 ps
T1102 /workspace/coverage/default/3.flash_ctrl_otp_reset.3966789466 Aug 03 06:23:59 PM PDT 24 Aug 03 06:25:51 PM PDT 24 60033000 ps
T1103 /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.1731859645 Aug 03 06:32:30 PM PDT 24 Aug 03 06:37:51 PM PDT 24 15256177500 ps
T1104 /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.387835352 Aug 03 06:27:21 PM PDT 24 Aug 03 06:29:16 PM PDT 24 10011612200 ps
T1105 /workspace/coverage/default/19.flash_ctrl_smoke.2961872715 Aug 03 06:30:13 PM PDT 24 Aug 03 06:31:52 PM PDT 24 49069400 ps
T1106 /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3281301309 Aug 03 06:21:53 PM PDT 24 Aug 03 06:23:39 PM PDT 24 10013906800 ps
T1107 /workspace/coverage/default/30.flash_ctrl_disable.486407756 Aug 03 06:31:50 PM PDT 24 Aug 03 06:32:12 PM PDT 24 13044300 ps
T339 /workspace/coverage/default/2.flash_ctrl_re_evict.2634358345 Aug 03 06:23:32 PM PDT 24 Aug 03 06:24:06 PM PDT 24 61411300 ps
T1108 /workspace/coverage/default/34.flash_ctrl_intr_rd.691790438 Aug 03 06:32:16 PM PDT 24 Aug 03 06:36:08 PM PDT 24 6333337600 ps
T86 /workspace/coverage/default/0.flash_ctrl_mid_op_rst.3032434187 Aug 03 06:21:17 PM PDT 24 Aug 03 06:22:35 PM PDT 24 4030012900 ps
T1109 /workspace/coverage/default/0.flash_ctrl_error_prog_win.2774987407 Aug 03 06:21:16 PM PDT 24 Aug 03 06:37:28 PM PDT 24 709815600 ps
T1110 /workspace/coverage/default/1.flash_ctrl_rw.3371200535 Aug 03 06:22:21 PM PDT 24 Aug 03 06:32:55 PM PDT 24 27627649000 ps
T136 /workspace/coverage/default/9.flash_ctrl_mp_regions.3077691091 Aug 03 06:27:05 PM PDT 24 Aug 03 06:36:35 PM PDT 24 19643480600 ps
T1111 /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.3971302021 Aug 03 06:25:41 PM PDT 24 Aug 03 06:25:55 PM PDT 24 26375900 ps
T1112 /workspace/coverage/default/29.flash_ctrl_intr_rd.1165701527 Aug 03 06:31:35 PM PDT 24 Aug 03 06:35:30 PM PDT 24 34554420500 ps
T195 /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3492300810 Aug 03 06:24:33 PM PDT 24 Aug 03 06:24:47 PM PDT 24 21929200 ps
T1113 /workspace/coverage/default/16.flash_ctrl_disable.2833433309 Aug 03 06:29:30 PM PDT 24 Aug 03 06:29:52 PM PDT 24 21166700 ps
T1114 /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.1781586393 Aug 03 06:23:03 PM PDT 24 Aug 03 07:03:38 PM PDT 24 568159038900 ps
T1115 /workspace/coverage/default/0.flash_ctrl_wo.2277182440 Aug 03 06:21:17 PM PDT 24 Aug 03 06:24:28 PM PDT 24 2740997900 ps
T1116 /workspace/coverage/default/7.flash_ctrl_smoke.850485523 Aug 03 06:26:14 PM PDT 24 Aug 03 06:28:20 PM PDT 24 83934900 ps
T1117 /workspace/coverage/default/12.flash_ctrl_ro.3782530268 Aug 03 06:28:15 PM PDT 24 Aug 03 06:30:09 PM PDT 24 3131384600 ps
T337 /workspace/coverage/default/13.flash_ctrl_re_evict.2186143526 Aug 03 06:28:33 PM PDT 24 Aug 03 06:29:06 PM PDT 24 128857100 ps
T187 /workspace/coverage/default/0.flash_ctrl_ro_serr.2042182433 Aug 03 06:21:24 PM PDT 24 Aug 03 06:24:05 PM PDT 24 10606411800 ps
T1118 /workspace/coverage/default/6.flash_ctrl_re_evict.3035718249 Aug 03 06:26:10 PM PDT 24 Aug 03 06:26:46 PM PDT 24 334958800 ps
T1119 /workspace/coverage/default/76.flash_ctrl_connect.4008770091 Aug 03 06:33:44 PM PDT 24 Aug 03 06:34:00 PM PDT 24 29185200 ps
T1120 /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.156171068 Aug 03 06:23:30 PM PDT 24 Aug 03 06:26:57 PM PDT 24 45511210900 ps
T1121 /workspace/coverage/default/4.flash_ctrl_serr_address.3764467839 Aug 03 06:25:07 PM PDT 24 Aug 03 06:26:13 PM PDT 24 1268637900 ps
T83 /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.2764784448 Aug 03 06:30:13 PM PDT 24 Aug 03 06:30:26 PM PDT 24 44072300 ps
T1122 /workspace/coverage/default/6.flash_ctrl_otp_reset.1118748499 Aug 03 06:25:47 PM PDT 24 Aug 03 06:27:38 PM PDT 24 41849700 ps
T1123 /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3431391629 Aug 03 06:24:29 PM PDT 24 Aug 03 06:27:46 PM PDT 24 50714808300 ps
T1124 /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.3687485564 Aug 03 06:30:10 PM PDT 24 Aug 03 06:30:42 PM PDT 24 92493900 ps
T1125 /workspace/coverage/default/17.flash_ctrl_sec_info_access.2204019298 Aug 03 06:29:52 PM PDT 24 Aug 03 06:30:44 PM PDT 24 331088600 ps
T1126 /workspace/coverage/default/72.flash_ctrl_otp_reset.3881151899 Aug 03 06:33:45 PM PDT 24 Aug 03 06:36:00 PM PDT 24 241535600 ps
T191 /workspace/coverage/default/4.flash_ctrl_rw_derr.1888307142 Aug 03 06:25:07 PM PDT 24 Aug 03 06:29:23 PM PDT 24 2091630500 ps
T1127 /workspace/coverage/default/15.flash_ctrl_phy_arb.4134139908 Aug 03 06:29:05 PM PDT 24 Aug 03 06:35:58 PM PDT 24 282869000 ps
T1128 /workspace/coverage/default/2.flash_ctrl_fetch_code.2017814189 Aug 03 06:23:07 PM PDT 24 Aug 03 06:23:29 PM PDT 24 335821700 ps
T1129 /workspace/coverage/default/22.flash_ctrl_rw_evict.4054389838 Aug 03 06:30:45 PM PDT 24 Aug 03 06:31:16 PM PDT 24 77167800 ps
T396 /workspace/coverage/default/3.flash_ctrl_sec_info_access.478664549 Aug 03 06:24:29 PM PDT 24 Aug 03 06:25:19 PM PDT 24 534339800 ps
T186 /workspace/coverage/default/0.flash_ctrl_rd_intg.422415023 Aug 03 06:21:39 PM PDT 24 Aug 03 06:22:09 PM PDT 24 70579200 ps
T64 /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.2668928704 Aug 03 06:21:44 PM PDT 24 Aug 03 06:21:58 PM PDT 24 45358900 ps
T1130 /workspace/coverage/default/49.flash_ctrl_disable.3347353732 Aug 03 06:33:18 PM PDT 24 Aug 03 06:33:40 PM PDT 24 34198100 ps
T1131 /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.1194460433 Aug 03 06:31:50 PM PDT 24 Aug 03 06:37:56 PM PDT 24 154926533500 ps
T1132 /workspace/coverage/default/1.flash_ctrl_invalid_op.191926506 Aug 03 06:22:15 PM PDT 24 Aug 03 06:23:18 PM PDT 24 3158350600 ps
T1133 /workspace/coverage/default/39.flash_ctrl_connect.2091466848 Aug 03 06:32:41 PM PDT 24 Aug 03 06:32:55 PM PDT 24 16326200 ps
T1134 /workspace/coverage/default/5.flash_ctrl_rw.963461993 Aug 03 06:25:33 PM PDT 24 Aug 03 06:35:19 PM PDT 24 8865076100 ps
T1135 /workspace/coverage/default/4.flash_ctrl_rw_evict.606266090 Aug 03 06:25:16 PM PDT 24 Aug 03 06:25:47 PM PDT 24 123018300 ps
T137 /workspace/coverage/default/18.flash_ctrl_rand_ops.2479519589 Aug 03 06:29:58 PM PDT 24 Aug 03 06:46:38 PM PDT 24 7695167400 ps
T1136 /workspace/coverage/default/30.flash_ctrl_rw_evict.3100595585 Aug 03 06:31:45 PM PDT 24 Aug 03 06:32:17 PM PDT 24 32870000 ps
T1137 /workspace/coverage/default/25.flash_ctrl_sec_info_access.2117247142 Aug 03 06:31:14 PM PDT 24 Aug 03 06:32:31 PM PDT 24 8471866700 ps
T124 /workspace/coverage/default/3.flash_ctrl_sec_cm.1980836728 Aug 03 06:24:30 PM PDT 24 Aug 03 07:47:03 PM PDT 24 8344917500 ps
T1138 /workspace/coverage/default/28.flash_ctrl_sec_info_access.3095291231 Aug 03 06:31:35 PM PDT 24 Aug 03 06:32:50 PM PDT 24 7946337800 ps
T65 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3778147677 Aug 03 05:01:21 PM PDT 24 Aug 03 05:01:38 PM PDT 24 38009100 ps
T257 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2075982358 Aug 03 05:01:38 PM PDT 24 Aug 03 05:01:51 PM PDT 24 63501400 ps
T258 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.4236129176 Aug 03 05:01:21 PM PDT 24 Aug 03 05:01:35 PM PDT 24 30498300 ps
T259 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2399136202 Aug 03 05:01:21 PM PDT 24 Aug 03 05:01:34 PM PDT 24 27341300 ps
T1139 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2957877054 Aug 03 05:01:15 PM PDT 24 Aug 03 05:01:29 PM PDT 24 61072200 ps
T66 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2282698061 Aug 03 05:01:25 PM PDT 24 Aug 03 05:07:54 PM PDT 24 349883500 ps
T320 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3989958265 Aug 03 05:01:23 PM PDT 24 Aug 03 05:01:36 PM PDT 24 65373400 ps
T1140 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2248355757 Aug 03 05:01:13 PM PDT 24 Aug 03 05:01:29 PM PDT 24 19424900 ps
T321 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3090450420 Aug 03 05:01:23 PM PDT 24 Aug 03 05:01:37 PM PDT 24 15875100 ps
T1141 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1251734281 Aug 03 05:01:12 PM PDT 24 Aug 03 05:01:29 PM PDT 24 24609200 ps
T322 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3775022802 Aug 03 05:01:33 PM PDT 24 Aug 03 05:01:47 PM PDT 24 17890500 ps
T324 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3518249809 Aug 03 05:01:12 PM PDT 24 Aug 03 05:01:26 PM PDT 24 15498100 ps
T117 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.664418814 Aug 03 05:01:26 PM PDT 24 Aug 03 05:01:46 PM PDT 24 130974700 ps
T1142 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1302995735 Aug 03 05:01:11 PM PDT 24 Aug 03 05:01:24 PM PDT 24 40458900 ps
T358 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3706811696 Aug 03 05:01:13 PM PDT 24 Aug 03 05:01:27 PM PDT 24 15318200 ps
T323 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2757945842 Aug 03 05:01:35 PM PDT 24 Aug 03 05:01:49 PM PDT 24 83238200 ps
T1143 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3665537446 Aug 03 05:01:15 PM PDT 24 Aug 03 05:01:29 PM PDT 24 43632000 ps
T67 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.307002147 Aug 03 05:01:13 PM PDT 24 Aug 03 05:01:30 PM PDT 24 1299943200 ps
T118 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2505723410 Aug 03 05:01:12 PM PDT 24 Aug 03 05:01:31 PM PDT 24 109593000 ps
T233 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4222317730 Aug 03 05:01:49 PM PDT 24 Aug 03 05:02:05 PM PDT 24 63530700 ps
T1144 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3937007664 Aug 03 05:01:24 PM PDT 24 Aug 03 05:01:38 PM PDT 24 27210100 ps
T250 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.474824564 Aug 03 05:01:05 PM PDT 24 Aug 03 05:01:51 PM PDT 24 157537700 ps
T209 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3531475070 Aug 03 05:01:22 PM PDT 24 Aug 03 05:16:38 PM PDT 24 3077078700 ps
T1145 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3887287435 Aug 03 05:01:17 PM PDT 24 Aug 03 05:01:35 PM PDT 24 32166900 ps
T217 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.235796743 Aug 03 05:01:16 PM PDT 24 Aug 03 05:01:35 PM PDT 24 86636100 ps
T234 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.277390911 Aug 03 05:01:08 PM PDT 24 Aug 03 05:01:23 PM PDT 24 20310700 ps
T1146 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3923852311 Aug 03 05:01:30 PM PDT 24 Aug 03 05:01:44 PM PDT 24 17452400 ps
T1147 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1504226046 Aug 03 05:01:14 PM PDT 24 Aug 03 05:01:30 PM PDT 24 32500500 ps
T235 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1360123403 Aug 03 05:01:15 PM PDT 24 Aug 03 05:01:34 PM PDT 24 162924800 ps
T236 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2926215328 Aug 03 05:01:11 PM PDT 24 Aug 03 05:01:43 PM PDT 24 958270000 ps
T237 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.733687499 Aug 03 05:01:17 PM PDT 24 Aug 03 05:01:32 PM PDT 24 98279800 ps
T1148 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1922962258 Aug 03 05:01:06 PM PDT 24 Aug 03 05:01:22 PM PDT 24 16013300 ps
T218 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3706349119 Aug 03 05:01:24 PM PDT 24 Aug 03 05:01:42 PM PDT 24 215800400 ps
T223 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.686881529 Aug 03 05:01:14 PM PDT 24 Aug 03 05:07:43 PM PDT 24 343124200 ps
T1149 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.376693418 Aug 03 05:01:06 PM PDT 24 Aug 03 05:01:20 PM PDT 24 18696000 ps
T219 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1349721320 Aug 03 05:01:16 PM PDT 24 Aug 03 05:01:36 PM PDT 24 1338675000 ps
T274 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2491286426 Aug 03 05:01:18 PM PDT 24 Aug 03 05:16:21 PM PDT 24 2754403400 ps
T1150 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2062114918 Aug 03 05:01:23 PM PDT 24 Aug 03 05:01:37 PM PDT 24 26474800 ps
T1151 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1058344303 Aug 03 05:01:19 PM PDT 24 Aug 03 05:01:33 PM PDT 24 18147700 ps
T1152 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.955640367 Aug 03 05:01:17 PM PDT 24 Aug 03 05:01:31 PM PDT 24 82342600 ps
T220 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.403911887 Aug 03 05:01:04 PM PDT 24 Aug 03 05:01:29 PM PDT 24 85034500 ps
T1153 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2839746171 Aug 03 05:01:10 PM PDT 24 Aug 03 05:01:26 PM PDT 24 18470700 ps
T238 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2759957969 Aug 03 05:01:13 PM PDT 24 Aug 03 05:01:30 PM PDT 24 82494500 ps
T1154 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2586484478 Aug 03 05:01:16 PM PDT 24 Aug 03 05:01:30 PM PDT 24 23712400 ps
T221 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2262209664 Aug 03 05:01:17 PM PDT 24 Aug 03 05:01:33 PM PDT 24 38064000 ps
T222 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1381922468 Aug 03 05:01:10 PM PDT 24 Aug 03 05:01:25 PM PDT 24 172733300 ps
T1155 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2299200777 Aug 03 05:01:14 PM PDT 24 Aug 03 05:01:28 PM PDT 24 21901700 ps
T225 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3183872738 Aug 03 05:01:13 PM PDT 24 Aug 03 05:16:17 PM PDT 24 801177500 ps
T224 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.4053049347 Aug 03 05:01:14 PM PDT 24 Aug 03 05:01:31 PM PDT 24 405294400 ps
T1156 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1992901053 Aug 03 05:01:24 PM PDT 24 Aug 03 05:01:37 PM PDT 24 50237100 ps
T1157 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3109274005 Aug 03 05:01:06 PM PDT 24 Aug 03 05:01:19 PM PDT 24 19720300 ps
T1158 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.379993463 Aug 03 05:01:19 PM PDT 24 Aug 03 05:01:32 PM PDT 24 42249800 ps
T239 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3005019866 Aug 03 05:01:31 PM PDT 24 Aug 03 05:02:05 PM PDT 24 57939800 ps
T240 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1385571530 Aug 03 05:01:16 PM PDT 24 Aug 03 05:01:53 PM PDT 24 958095600 ps
T241 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2952429979 Aug 03 05:01:07 PM PDT 24 Aug 03 05:01:27 PM PDT 24 160064500 ps
T251 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.183665951 Aug 03 05:01:22 PM PDT 24 Aug 03 05:01:38 PM PDT 24 36809800 ps
T1159 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.749875216 Aug 03 05:01:23 PM PDT 24 Aug 03 05:01:37 PM PDT 24 15922000 ps
T1160 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.503053953 Aug 03 05:01:11 PM PDT 24 Aug 03 05:01:27 PM PDT 24 39898900 ps
T1161 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2365091317 Aug 03 05:01:36 PM PDT 24 Aug 03 05:01:49 PM PDT 24 137836500 ps
T298 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.58616824 Aug 03 05:01:04 PM PDT 24 Aug 03 05:01:59 PM PDT 24 6568784700 ps
T248 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.475170619 Aug 03 05:01:13 PM PDT 24 Aug 03 05:01:32 PM PDT 24 52398600 ps
T299 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3538373889 Aug 03 05:01:15 PM PDT 24 Aug 03 05:02:05 PM PDT 24 1562180000 ps
T300 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3448255578 Aug 03 05:01:10 PM PDT 24 Aug 03 05:01:28 PM PDT 24 68665800 ps
T273 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2475473261 Aug 03 05:01:08 PM PDT 24 Aug 03 05:13:50 PM PDT 24 2059186100 ps
T264 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1767592297 Aug 03 05:01:11 PM PDT 24 Aug 03 05:01:30 PM PDT 24 81396400 ps
T228 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2402504794 Aug 03 05:01:14 PM PDT 24 Aug 03 05:01:28 PM PDT 24 22878600 ps
T1162 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1179880826 Aug 03 05:01:08 PM PDT 24 Aug 03 05:01:27 PM PDT 24 55852900 ps
T265 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1964545751 Aug 03 05:01:20 PM PDT 24 Aug 03 05:07:48 PM PDT 24 706148600 ps
T301 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3468640408 Aug 03 05:01:15 PM PDT 24 Aug 03 05:01:30 PM PDT 24 56907600 ps
T1163 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3448742726 Aug 03 05:01:17 PM PDT 24 Aug 03 05:01:35 PM PDT 24 171828300 ps
T1164 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1705247291 Aug 03 05:01:09 PM PDT 24 Aug 03 05:01:23 PM PDT 24 28173600 ps
T1165 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.679812108 Aug 03 05:01:03 PM PDT 24 Aug 03 05:01:21 PM PDT 24 124701700 ps
T1166 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1572853867 Aug 03 05:01:12 PM PDT 24 Aug 03 05:01:28 PM PDT 24 17535300 ps
T255 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.4128592617 Aug 03 05:01:21 PM PDT 24 Aug 03 05:01:38 PM PDT 24 132811500 ps
T1167 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1199947252 Aug 03 05:01:15 PM PDT 24 Aug 03 05:01:34 PM PDT 24 256845900 ps
T229 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3826771024 Aug 03 05:01:12 PM PDT 24 Aug 03 05:01:26 PM PDT 24 29359400 ps
T1168 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1254268404 Aug 03 05:01:20 PM PDT 24 Aug 03 05:01:33 PM PDT 24 57144700 ps
T1169 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1272233467 Aug 03 05:01:33 PM PDT 24 Aug 03 05:01:47 PM PDT 24 35936800 ps
T1170 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3807003851 Aug 03 05:01:20 PM PDT 24 Aug 03 05:01:38 PM PDT 24 169240300 ps
T1171 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4169326076 Aug 03 05:01:48 PM PDT 24 Aug 03 05:02:06 PM PDT 24 125125800 ps
T263 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2826031957 Aug 03 05:01:15 PM PDT 24 Aug 03 05:01:35 PM PDT 24 405370200 ps
T230 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2973793672 Aug 03 05:01:07 PM PDT 24 Aug 03 05:01:21 PM PDT 24 97699600 ps
T1172 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3356960550 Aug 03 05:01:03 PM PDT 24 Aug 03 05:01:39 PM PDT 24 1255546900 ps
T1173 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2882255669 Aug 03 05:01:12 PM PDT 24 Aug 03 05:01:26 PM PDT 24 55046200 ps
T1174 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3985670873 Aug 03 05:01:03 PM PDT 24 Aug 03 05:01:16 PM PDT 24 15659900 ps
T1175 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1491590316 Aug 03 05:01:32 PM PDT 24 Aug 03 05:01:46 PM PDT 24 111539700 ps
T271 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1860010776 Aug 03 05:01:23 PM PDT 24 Aug 03 05:14:06 PM PDT 24 3518140400 ps
T253 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4212584495 Aug 03 05:01:18 PM PDT 24 Aug 03 05:01:38 PM PDT 24 188622100 ps
T1176 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.428813178 Aug 03 05:01:07 PM PDT 24 Aug 03 05:01:21 PM PDT 24 98632300 ps
T1177 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.992959828 Aug 03 05:01:13 PM PDT 24 Aug 03 05:01:28 PM PDT 24 207144800 ps
T1178 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.528089843 Aug 03 05:01:19 PM PDT 24 Aug 03 05:01:35 PM PDT 24 90206100 ps
T1179 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.870739284 Aug 03 05:01:18 PM PDT 24 Aug 03 05:01:38 PM PDT 24 368490500 ps
T1180 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.54306565 Aug 03 05:01:16 PM PDT 24 Aug 03 05:01:29 PM PDT 24 17922000 ps
T1181 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.4211562913 Aug 03 05:01:06 PM PDT 24 Aug 03 05:01:22 PM PDT 24 14883300 ps
T1182 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1987002172 Aug 03 05:01:11 PM PDT 24 Aug 03 05:01:25 PM PDT 24 58711200 ps
T1183 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2547150010 Aug 03 05:01:07 PM PDT 24 Aug 03 05:01:23 PM PDT 24 63914700 ps
T1184 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2948480873 Aug 03 05:01:08 PM PDT 24 Aug 03 05:01:22 PM PDT 24 51410000 ps
T1185 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1735293464 Aug 03 05:01:16 PM PDT 24 Aug 03 05:01:42 PM PDT 24 95543000 ps
T1186 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2462703923 Aug 03 05:01:21 PM PDT 24 Aug 03 05:01:36 PM PDT 24 12794200 ps
T1187 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2897124163 Aug 03 05:01:14 PM PDT 24 Aug 03 05:01:28 PM PDT 24 48618800 ps
T1188 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.733502668 Aug 03 05:01:09 PM PDT 24 Aug 03 05:01:26 PM PDT 24 161449300 ps
T256 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3214894854 Aug 03 05:01:07 PM PDT 24 Aug 03 05:01:23 PM PDT 24 300659600 ps
T270 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3320603625 Aug 03 05:01:13 PM PDT 24 Aug 03 05:16:20 PM PDT 24 325026000 ps
T269 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2484199576 Aug 03 05:01:18 PM PDT 24 Aug 03 05:14:02 PM PDT 24 781670000 ps
T266 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.737621476 Aug 03 05:01:12 PM PDT 24 Aug 03 05:01:30 PM PDT 24 84906500 ps
T1189 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2643022387 Aug 03 05:01:18 PM PDT 24 Aug 03 05:01:32 PM PDT 24 21621000 ps
T1190 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.697215202 Aug 03 05:01:15 PM PDT 24 Aug 03 05:01:31 PM PDT 24 29004600 ps
T1191 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1786355805 Aug 03 05:01:07 PM PDT 24 Aug 03 05:01:21 PM PDT 24 17646400 ps
T275 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2275695312 Aug 03 05:01:06 PM PDT 24 Aug 03 05:08:49 PM PDT 24 712978500 ps
T1192 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2232554018 Aug 03 05:01:20 PM PDT 24 Aug 03 05:01:36 PM PDT 24 292667200 ps
T1193 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1768150814 Aug 03 05:01:03 PM PDT 24 Aug 03 05:01:17 PM PDT 24 11240400 ps
T1194 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.736233646 Aug 03 05:01:15 PM PDT 24 Aug 03 05:02:04 PM PDT 24 5772949100 ps
T252 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2690076879 Aug 03 05:01:17 PM PDT 24 Aug 03 05:01:38 PM PDT 24 247420200 ps
T1195 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.4002100479 Aug 03 05:01:01 PM PDT 24 Aug 03 05:01:40 PM PDT 24 42533300 ps
T1196 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3955998424 Aug 03 05:01:24 PM PDT 24 Aug 03 05:01:38 PM PDT 24 45648800 ps
T1197 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4014088174 Aug 03 05:01:48 PM PDT 24 Aug 03 05:02:04 PM PDT 24 149532000 ps
T1198 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.975746429 Aug 03 05:01:23 PM PDT 24 Aug 03 05:01:37 PM PDT 24 27788500 ps
T1199 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3614306538 Aug 03 05:01:08 PM PDT 24 Aug 03 05:01:42 PM PDT 24 65417300 ps
T1200 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2263785939 Aug 03 05:01:23 PM PDT 24 Aug 03 05:01:37 PM PDT 24 14887700 ps
T1201 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.568812594 Aug 03 05:01:24 PM PDT 24 Aug 03 05:01:38 PM PDT 24 16974500 ps
T1202 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.600032849 Aug 03 05:01:25 PM PDT 24 Aug 03 05:01:39 PM PDT 24 238397400 ps
T1203 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2088185219 Aug 03 05:01:03 PM PDT 24 Aug 03 05:02:34 PM PDT 24 7810985700 ps
T1204 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2601885902 Aug 03 05:01:12 PM PDT 24 Aug 03 05:01:29 PM PDT 24 27076900 ps
T1205 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3641459911 Aug 03 05:01:13 PM PDT 24 Aug 03 05:01:26 PM PDT 24 20201900 ps
T362 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.18702419 Aug 03 05:01:23 PM PDT 24 Aug 03 05:09:10 PM PDT 24 525181500 ps
T1206 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.826526822 Aug 03 05:01:18 PM PDT 24 Aug 03 05:01:34 PM PDT 24 50548100 ps
T1207 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.4051499740 Aug 03 05:01:03 PM PDT 24 Aug 03 05:01:18 PM PDT 24 12954700 ps
T1208 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3504105280 Aug 03 05:01:11 PM PDT 24 Aug 03 05:01:26 PM PDT 24 172454600 ps
T277 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.111547248 Aug 03 05:01:12 PM PDT 24 Aug 03 05:07:44 PM PDT 24 448416500 ps
T1209 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1176360877 Aug 03 05:01:15 PM PDT 24 Aug 03 05:01:29 PM PDT 24 37927600 ps
T1210 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1541402402 Aug 03 05:01:24 PM PDT 24 Aug 03 05:01:38 PM PDT 24 44294000 ps
T1211 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1243855510 Aug 03 05:01:20 PM PDT 24 Aug 03 05:01:34 PM PDT 24 51926900 ps
T1212 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.160863030 Aug 03 05:01:04 PM PDT 24 Aug 03 05:01:20 PM PDT 24 31305300 ps
T302 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3162080202 Aug 03 05:01:23 PM PDT 24 Aug 03 05:01:41 PM PDT 24 197742900 ps
T1213 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2551362179 Aug 03 05:01:14 PM PDT 24 Aug 03 05:01:30 PM PDT 24 40215800 ps
T1214 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3385066922 Aug 03 05:01:12 PM PDT 24 Aug 03 05:02:17 PM PDT 24 1291461100 ps
T1215 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.250486132 Aug 03 05:01:20 PM PDT 24 Aug 03 05:01:38 PM PDT 24 758945900 ps
T1216 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1242432481 Aug 03 05:01:26 PM PDT 24 Aug 03 05:01:44 PM PDT 24 544754400 ps
T1217 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3010000417 Aug 03 05:01:11 PM PDT 24 Aug 03 05:01:27 PM PDT 24 60644300 ps
T1218 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.4098072391 Aug 03 05:01:17 PM PDT 24 Aug 03 05:01:31 PM PDT 24 16598900 ps
T1219 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.253155458 Aug 03 05:01:25 PM PDT 24 Aug 03 05:01:38 PM PDT 24 32802200 ps
T359 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3777426106 Aug 03 05:01:16 PM PDT 24 Aug 03 05:08:57 PM PDT 24 2569787600 ps
T1220 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1298052807 Aug 03 05:01:14 PM PDT 24 Aug 03 05:01:28 PM PDT 24 17775600 ps
T1221 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1106088491 Aug 03 05:01:19 PM PDT 24 Aug 03 05:01:34 PM PDT 24 42020700 ps
T1222 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3056059126 Aug 03 05:01:10 PM PDT 24 Aug 03 05:01:23 PM PDT 24 47270500 ps
T1223 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.804085488 Aug 03 05:01:22 PM PDT 24 Aug 03 05:01:36 PM PDT 24 30365800 ps
T363 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2518185271 Aug 03 05:01:13 PM PDT 24 Aug 03 05:09:00 PM PDT 24 428255100 ps
T1224 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.851148459 Aug 03 05:01:13 PM PDT 24 Aug 03 05:01:29 PM PDT 24 38057900 ps
T1225 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.336439053 Aug 03 05:01:04 PM PDT 24 Aug 03 05:01:23 PM PDT 24 399799800 ps
T254 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1971853650 Aug 03 05:01:10 PM PDT 24 Aug 03 05:01:26 PM PDT 24 296174100 ps
T1226 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3876838272 Aug 03 05:01:23 PM PDT 24 Aug 03 05:01:39 PM PDT 24 44426500 ps
T364 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3982896311 Aug 03 05:01:08 PM PDT 24 Aug 03 05:08:46 PM PDT 24 1174735900 ps
T1227 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3309543886 Aug 03 05:01:17 PM PDT 24 Aug 03 05:01:36 PM PDT 24 39391500 ps
T1228 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1004590937 Aug 03 05:01:15 PM PDT 24 Aug 03 05:01:34 PM PDT 24 353228800 ps
T260 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.434007171 Aug 03 05:01:22 PM PDT 24 Aug 03 05:01:42 PM PDT 24 65410300 ps
T1229 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2884485585 Aug 03 05:01:22 PM PDT 24 Aug 03 05:01:39 PM PDT 24 57258400 ps
T303 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3951690921 Aug 03 05:01:30 PM PDT 24 Aug 03 05:01:47 PM PDT 24 268382800 ps
T1230 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.4019993476 Aug 03 05:01:20 PM PDT 24 Aug 03 05:01:34 PM PDT 24 44470400 ps
T1231 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1831042357 Aug 03 05:01:26 PM PDT 24 Aug 03 05:01:40 PM PDT 24 78425500 ps
T1232 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3559194203 Aug 03 05:01:23 PM PDT 24 Aug 03 05:01:37 PM PDT 24 31657500 ps
T1233 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1160834765 Aug 03 05:01:22 PM PDT 24 Aug 03 05:01:36 PM PDT 24 15714800 ps
T1234 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4241934529 Aug 03 05:01:10 PM PDT 24 Aug 03 05:01:40 PM PDT 24 117088200 ps
T1235 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2456203577 Aug 03 05:01:15 PM PDT 24 Aug 03 05:01:46 PM PDT 24 34349000 ps
T304 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2758322925 Aug 03 05:01:23 PM PDT 24 Aug 03 05:01:41 PM PDT 24 401675100 ps
T1236 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3342991751 Aug 03 05:01:19 PM PDT 24 Aug 03 05:08:50 PM PDT 24 1615374800 ps
T1237 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3752620171 Aug 03 05:01:25 PM PDT 24 Aug 03 05:01:39 PM PDT 24 78010600 ps
T1238 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1883955896 Aug 03 05:01:26 PM PDT 24 Aug 03 05:01:40 PM PDT 24 43787300 ps
T1239 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3668317461 Aug 03 05:01:06 PM PDT 24 Aug 03 05:01:24 PM PDT 24 47471100 ps
T1240 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.308531592 Aug 03 05:01:38 PM PDT 24 Aug 03 05:01:52 PM PDT 24 40679000 ps
T1241 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1792081895 Aug 03 05:01:24 PM PDT 24 Aug 03 05:01:38 PM PDT 24 55122700 ps
T1242 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2147849811 Aug 03 05:01:10 PM PDT 24 Aug 03 05:01:24 PM PDT 24 17421600 ps
T1243 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3255640803 Aug 03 05:01:07 PM PDT 24 Aug 03 05:01:26 PM PDT 24 402531500 ps
T1244 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3972403847 Aug 03 05:01:16 PM PDT 24 Aug 03 05:01:31 PM PDT 24 19622400 ps
T1245 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1942800386 Aug 03 05:01:21 PM PDT 24 Aug 03 05:01:37 PM PDT 24 29875300 ps
T268 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.173161465 Aug 03 05:01:13 PM PDT 24 Aug 03 05:01:29 PM PDT 24 109028300 ps
T1246 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2863965926 Aug 03 05:01:13 PM PDT 24 Aug 03 05:01:30 PM PDT 24 399577000 ps
T1247 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2061209899 Aug 03 05:01:26 PM PDT 24 Aug 03 05:01:42 PM PDT 24 43976300 ps
T305 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1886346534 Aug 03 05:01:06 PM PDT 24 Aug 03 05:01:21 PM PDT 24 359650900 ps
T306 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1979812934 Aug 03 05:01:12 PM PDT 24 Aug 03 05:02:19 PM PDT 24 6410127000 ps
T231 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3574314996 Aug 03 05:01:15 PM PDT 24 Aug 03 05:01:29 PM PDT 24 17128500 ps
T1248 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2466999298 Aug 03 05:01:12 PM PDT 24 Aug 03 05:01:43 PM PDT 24 137498700 ps
T261 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3399980279 Aug 03 05:01:09 PM PDT 24 Aug 03 05:01:28 PM PDT 24 112203800 ps
T1249 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2089999303 Aug 03 05:01:30 PM PDT 24 Aug 03 05:01:46 PM PDT 24 48495600 ps
T1250 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1237159621 Aug 03 05:01:21 PM PDT 24 Aug 03 05:01:35 PM PDT 24 97487700 ps
T1251 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2354234201 Aug 03 05:01:06 PM PDT 24 Aug 03 05:01:20 PM PDT 24 29449200 ps
T1252 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1970081797 Aug 03 05:01:07 PM PDT 24 Aug 03 05:02:04 PM PDT 24 660215800 ps
T267 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.892612704 Aug 03 05:01:24 PM PDT 24 Aug 03 05:01:41 PM PDT 24 67204800 ps
T276 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1329515943 Aug 03 05:01:12 PM PDT 24 Aug 03 05:08:48 PM PDT 24 1728397000 ps
T307 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.945761093 Aug 03 05:01:10 PM PDT 24 Aug 03 05:01:29 PM PDT 24 1201552600 ps
T262 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1934004462 Aug 03 05:01:17 PM PDT 24 Aug 03 05:01:36 PM PDT 24 435009300 ps
T1253 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3942281864 Aug 03 05:01:12 PM PDT 24 Aug 03 05:01:29 PM PDT 24 14653700 ps
T1254 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.954157143 Aug 03 05:01:48 PM PDT 24 Aug 03 05:02:02 PM PDT 24 77559400 ps
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