Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	308585	1		T1	1		T2	2		T3	2
all_values[1]	308585	1		T1	1		T2	2		T3	2
all_values[2]	308585	1		T1	1		T2	2		T3	2
all_values[3]	308585	1		T1	1		T2	2		T3	2
all_values[4]	308585	1		T1	1		T2	2		T3	2
all_values[5]	308585	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	623562	1		T1	6		T2	12		T3	12
auto[1]	1227948	1		T21	28316		T26	5664		T32	4248

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	905604	1		T1	4		T2	7		T3	7
auto[1]	945906	1		T1	2		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	308432	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	153	1		T250	3		T251	4		T252	3
all_values[1]	auto[0]	auto[1]	308429	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	156	1		T250	1		T251	4		T252	4
all_values[2]	auto[0]	auto[0]	1609	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	67	1		T250	3		T252	2		T310	2
all_values[2]	auto[1]	auto[0]	306850	1		T21	7079		T26	1416		T32	1062
all_values[2]	auto[1]	auto[1]	59	1		T250	1		T252	3		T310	2
all_values[3]	auto[0]	auto[0]	1613	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	60	1		T250	2		T251	1		T252	3
all_values[3]	auto[1]	auto[0]	79684	1		T21	21		T26	1416		T32	531
all_values[3]	auto[1]	auto[1]	227228	1		T21	7058		T32	531		T35	3326
all_values[4]	auto[0]	auto[0]	1151	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	517	1		T2	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	206280	1		T21	6497		T26	1		T32	531
all_values[4]	auto[1]	auto[1]	100637	1		T21	582		T26	1415		T32	531
all_values[5]	auto[0]	auto[0]	1588	1		T1	1		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	96	1		T4	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	306829	1		T21	7079		T26	1416		T32	1062
all_values[5]	auto[1]	auto[1]	72	1		T251	2		T313	1		T314	2