Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	245191	1		T2	600		T3	11		T4	802
auto[FlashEraseBank]	265721	1		T3	4		T4	682		T16	5

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	253912	1		T2	200		T3	4		T4	679
auto[FlashOpProgram]	236105	1		T2	100		T3	6		T4	805
auto[FlashOpErase]	16895	1		T2	100		T3	5		T5	5
auto[FlashOpInvalid]	4000	1		T2	200		T143	200		T135	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	253912	1		T2	200		T3	4		T4	679
op[FlashOpProgram]	236105	1		T2	100		T3	6		T4	805
op[FlashOpErase]	16895	1		T2	100		T3	5		T5	5
read_erase_read	541	1		T3	1		T5	2		T19	4
read_prog_read	829	1		T4	5		T16	1		T5	13

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	362398	1		T2	582		T3	15		T4	1302
auto[FlashPartInfo]	144987	1		T2	18		T4	176		T16	6
auto[FlashPartInfo1]	798	1		T4	1		T5	15		T6	3
auto[FlashPartInfo2]	2729	1		T4	5		T5	10		T6	8

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	179168	1		T2	194		T3	4		T4	584
auto[FlashPartData]	auto[FlashOpProgram]	175753	1		T2	97		T3	6		T4	718
auto[FlashPartData]	auto[FlashOpErase]	3577	1		T2	97		T3	5		T5	3
auto[FlashPartData]	auto[FlashOpInvalid]	3900	1		T2	194		T143	196		T135	194
auto[FlashPartInfo]	auto[FlashOpRead]	72348	1		T2	6		T4	92		T16	6
auto[FlashPartInfo]	auto[FlashOpProgram]	59265	1		T2	3		T4	84		T5	11
auto[FlashPartInfo]	auto[FlashOpErase]	13286	1		T2	3		T5	1		T59	4
auto[FlashPartInfo]	auto[FlashOpInvalid]	88	1		T2	6		T143	4		T135	6
auto[FlashPartInfo1]	auto[FlashOpRead]	619	1		T4	1		T5	15		T6	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T123	1		T125	1		T147	32
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T123	1		T124	1		T125	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T123	2		T125	2		T382	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1777	1		T4	2		T5	6		T6	8
auto[FlashPartInfo2]	auto[FlashOpProgram]	922	1		T4	3		T5	3		T18	5
auto[FlashPartInfo2]	auto[FlashOpErase]	26	1		T5	1		T154	1		T383	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T384	2		T385	2		-	-