Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33399	1		T2	400		T3	5		T5	4
auto[1]	81	1		T38	1		T36	1		T264	1
auto[2]	67	1		T196	1		T133	12		T386	1
auto[3]	305	1		T16	1		T24	1		T196	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8471	1		T2	100		T3	2		T5	1
evic_idx[1]	8461	1		T2	100		T3	1		T16	1
evic_idx[2]	8461	1		T2	100		T3	1		T5	1
evic_idx[3]	8459	1		T2	100		T3	1		T5	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	32895	1		T2	400		T93	604		T94	456
evic_op[2]	365	1		T3	1		T16	1		T24	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	8138	1		T2	100		T93	151		T94	114
evic_idx[0]	evic_op[1]	auto[1]	19	1		T383	3		T387	1		T388	3
evic_idx[0]	evic_op[1]	auto[2]	8	1		T388	1		T389	2		T390	3
evic_idx[0]	evic_op[1]	auto[3]	65	1		T268	1		T383	4		T387	1
evic_idx[0]	evic_op[2]	auto[0]	68	1		T3	1		T45	4		T209	2
evic_idx[0]	evic_op[2]	auto[1]	4	1		T38	1		T391	1		T392	1
evic_idx[0]	evic_op[2]	auto[2]	7	1		T196	1		T393	1		T394	1
evic_idx[0]	evic_op[2]	auto[3]	14	1		T201	1		T395	1		T396	1
evic_idx[1]	evic_op[1]	auto[0]	8136	1		T2	100		T93	151		T94	114
evic_idx[1]	evic_op[1]	auto[1]	13	1		T383	5		T387	1		T388	1
evic_idx[1]	evic_op[1]	auto[2]	10	1		T388	1		T389	3		T390	4
evic_idx[1]	evic_op[1]	auto[3]	62	1		T268	2		T383	2		T387	2
evic_idx[1]	evic_op[2]	auto[0]	67	1		T45	4		T209	2		T144	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T36	1		T118	1		T392	1
evic_idx[1]	evic_op[2]	auto[2]	5	1		T386	1		T397	1		T398	1
evic_idx[1]	evic_op[2]	auto[3]	16	1		T16	1		T201	1		T265	1
evic_idx[2]	evic_op[1]	auto[0]	8140	1		T2	100		T93	151		T94	114
evic_idx[2]	evic_op[1]	auto[1]	16	1		T383	6		T387	1		T388	1
evic_idx[2]	evic_op[1]	auto[2]	7	1		T388	1		T399	1		T389	1
evic_idx[2]	evic_op[1]	auto[3]	64	1		T268	1		T383	2		T387	3
evic_idx[2]	evic_op[2]	auto[0]	71	1		T45	4		T209	2		T144	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T264	1		T392	1		T380	1
evic_idx[2]	evic_op[2]	auto[2]	5	1		T400	1		T394	2		T401	2
evic_idx[2]	evic_op[2]	auto[3]	6	1		T24	1		T196	1		T201	1
evic_idx[3]	evic_op[1]	auto[0]	8138	1		T2	100		T93	151		T94	114
evic_idx[3]	evic_op[1]	auto[1]	14	1		T383	4		T387	1		T388	2
evic_idx[3]	evic_op[1]	auto[2]	6	1		T388	1		T399	1		T389	1
evic_idx[3]	evic_op[1]	auto[3]	59	1		T268	2		T383	2		T387	2
evic_idx[3]	evic_op[2]	auto[0]	65	1		T45	4		T209	2		T144	1
evic_idx[3]	evic_op[2]	auto[1]	7	1		T402	1		T80	1		T393	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T400	1		T401	2		-	-
evic_idx[3]	evic_op[2]	auto[3]	19	1		T201	1		T403	1		T291	1