Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
4931 | 
1 | 
 | 
T48 | 
171 | 
 | 
T49 | 
114 | 
 | 
T50 | 
120 | 
| instr_types[0] | 
6034 | 
1 | 
 | 
T48 | 
211 | 
 | 
T49 | 
277 | 
 | 
T50 | 
282 | 
| instr_types[1] | 
4109945 | 
1 | 
 | 
T3 | 
191 | 
 | 
T4 | 
16605 | 
 | 
T16 | 
10 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4118603 | 
1 | 
 | 
T3 | 
191 | 
 | 
T4 | 
16605 | 
 | 
T16 | 
10 | 
| auto[1] | 
2307 | 
1 | 
 | 
T48 | 
142 | 
 | 
T49 | 
319 | 
 | 
T50 | 
185 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
4487 | 
1 | 
 | 
T48 | 
128 | 
 | 
T49 | 
76 | 
 | 
T50 | 
62 | 
| auto[0] | 
instr_types[0] | 
5231 | 
1 | 
 | 
T48 | 
198 | 
 | 
T49 | 
159 | 
 | 
T50 | 
217 | 
| auto[0] | 
instr_types[1] | 
4108885 | 
1 | 
 | 
T3 | 
191 | 
 | 
T4 | 
16605 | 
 | 
T16 | 
10 | 
| auto[1] | 
others | 
444 | 
1 | 
 | 
T48 | 
43 | 
 | 
T49 | 
38 | 
 | 
T50 | 
58 | 
| auto[1] | 
instr_types[0] | 
803 | 
1 | 
 | 
T48 | 
13 | 
 | 
T49 | 
118 | 
 | 
T50 | 
65 | 
| auto[1] | 
instr_types[1] | 
1060 | 
1 | 
 | 
T48 | 
86 | 
 | 
T49 | 
163 | 
 | 
T50 | 
62 |