Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	29660	1		T21	2188		T316	2397		T317	2744
rd_lvl[2]	22120	1		T21	1134		T316	1243		T317	2678
rd_lvl[3]	20517	1		T21	584		T134	969		T318	1000
rd_lvl[4]	35179	1		T21	538		T134	450		T211	882
rd_lvl[5]	14138	1		T21	387		T159	2679		T134	32
rd_lvl[6]	12430	1		T21	98		T159	2730		T134	48
rd_lvl[7]	7406	1		T21	269		T35	1804		T134	1
rd_lvl[8]	18610	1		T21	242		T35	1511		T319	2196
rd_lvl[9]	10293	1		T21	346		T35	11		T34	417
rd_lvl[10]	10549	1		T21	124		T134	1		T34	495
rd_lvl[11]	4128	1		T21	56		T316	3		T320	197
rd_lvl[12]	2447	1		T21	2		T32	333		T33	275
rd_lvl[13]	2439	1		T21	1		T32	196		T33	242
rd_lvl[14]	8394	1		T21	55		T321	62		T316	4
rd_lvl[15]	3333	1		T32	2		T33	14		T321	26