Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	308585	1		T1	1		T2	2		T3	2
all_pins[1]	308585	1		T1	1		T2	2		T3	2
all_pins[2]	308585	1		T1	1		T2	2		T3	2
all_pins[3]	308585	1		T1	1		T2	2		T3	2
all_pins[4]	308585	1		T1	1		T2	2		T3	2
all_pins[5]	308585	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1530313	1		T1	6		T2	12		T3	12
values[0x1]	321197	1		T21	6645		T26	1415		T32	1062
transitions[0x0=>0x1]	285775	1		T21	6045		T26	1415		T32	1062
transitions[0x1=>0x0]	285766	1		T21	6045		T26	1415		T32	1062

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	308432	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	153	1		T250	3		T251	4		T252	3
all_pins[0]	transitions[0x0=>0x1]	87	1		T250	3		T252	3		T310	2
all_pins[0]	transitions[0x1=>0x0]	90	1		T250	1		T252	4		T310	3
all_pins[1]	values[0x0]	308429	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	156	1		T250	1		T251	4		T252	4
all_pins[1]	transitions[0x0=>0x1]	125	1		T251	4		T252	3		T310	4
all_pins[1]	transitions[0x1=>0x0]	3502	1		T326	1102		T327	1188		T328	1
all_pins[2]	values[0x0]	305052	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	3533	1		T326	1102		T327	1188		T328	1
all_pins[2]	transitions[0x0=>0x1]	49	1		T250	1		T252	3		T310	2
all_pins[2]	transitions[0x1=>0x0]	202311	1		T21	6024		T32	531		T35	3326
all_pins[3]	values[0x0]	102790	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	205795	1		T21	6024		T32	531		T35	3326
all_pins[3]	transitions[0x0=>0x1]	174013	1		T21	5424		T32	531		T35	3326
all_pins[3]	transitions[0x1=>0x0]	79706	1		T21	21		T26	1415		T32	531
all_pins[4]	values[0x0]	197097	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	111488	1		T21	621		T26	1415		T32	531
all_pins[4]	transitions[0x0=>0x1]	111475	1		T21	621		T26	1415		T32	531
all_pins[4]	transitions[0x1=>0x0]	59	1		T251	2		T313	1		T314	2
all_pins[5]	values[0x0]	308513	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	72	1		T251	2		T313	1		T314	2
all_pins[5]	transitions[0x0=>0x1]	26	1		T314	1		T329	1		T330	2
all_pins[5]	transitions[0x1=>0x0]	98	1		T250	3		T251	1		T252	3