Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T250	7		T251	4		T252	7
all_values[1]	269	1		T250	7		T251	4		T252	7
all_values[2]	269	1		T250	7		T251	4		T252	7
all_values[3]	269	1		T250	7		T251	4		T252	7
all_values[4]	269	1		T250	7		T251	4		T252	7
all_values[5]	269	1		T250	7		T251	4		T252	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	881	1		T250	24		T251	16		T252	27
auto[1]	733	1		T250	18		T251	8		T252	15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	518	1		T250	11		T251	8		T252	11
auto[1]	1096	1		T250	31		T251	16		T252	31

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	935	1		T250	22		T251	14		T252	18
auto[1]	679	1		T250	20		T251	10		T252	24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	91	1		T250	1		T251	1		T252	2
all_values[0]	auto[0]	auto[1]	auto[1]	65	1		T250	2		T251	1		T310	1
all_values[0]	auto[1]	auto[0]	auto[1]	45	1		T250	2		T251	1		T252	3
all_values[0]	auto[1]	auto[1]	auto[1]	68	1		T250	2		T251	1		T252	2
all_values[1]	auto[0]	auto[0]	auto[1]	85	1		T250	6		T251	1		T252	2
all_values[1]	auto[0]	auto[1]	auto[1]	69	1		T250	1		T251	1		T252	2
all_values[1]	auto[1]	auto[0]	auto[1]	67	1		T251	1		T252	2		T310	3
all_values[1]	auto[1]	auto[1]	auto[1]	48	1		T251	1		T252	1		T310	1
all_values[2]	auto[0]	auto[0]	auto[0]	88	1		T250	1		T251	4		T252	2
all_values[2]	auto[0]	auto[1]	auto[0]	55	1		T250	2		T310	2		T311	1
all_values[2]	auto[1]	auto[0]	auto[1]	66	1		T250	2		T252	2		T310	2
all_values[2]	auto[1]	auto[1]	auto[1]	60	1		T250	2		T252	3		T310	2
all_values[3]	auto[0]	auto[0]	auto[0]	84	1		T250	3		T252	1		T310	1
all_values[3]	auto[0]	auto[1]	auto[0]	75	1		T250	1		T251	1		T252	1
all_values[3]	auto[1]	auto[0]	auto[1]	63	1		T250	2		T251	2		T252	3
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T250	1		T251	1		T252	2
all_values[4]	auto[0]	auto[0]	auto[0]	69	1		T250	1		T251	1		T252	4
all_values[4]	auto[0]	auto[0]	auto[1]	21	1		T251	1		T311	1		T312	2
all_values[4]	auto[0]	auto[1]	auto[0]	50	1		T252	1		T310	2		T311	1
all_values[4]	auto[0]	auto[1]	auto[1]	24	1		T250	1		T311	1		T313	1
all_values[4]	auto[1]	auto[0]	auto[1]	57	1		T250	2		T251	2		T252	2
all_values[4]	auto[1]	auto[1]	auto[1]	48	1		T250	3		T310	1		T313	1
all_values[5]	auto[0]	auto[0]	auto[0]	52	1		T250	1		T251	2		T252	1
all_values[5]	auto[0]	auto[0]	auto[1]	29	1		T252	1		T311	1		T313	1
all_values[5]	auto[0]	auto[1]	auto[0]	45	1		T250	2		T252	1		T310	6
all_values[5]	auto[0]	auto[1]	auto[1]	33	1		T251	1		T314	1		T315	1
all_values[5]	auto[1]	auto[0]	auto[1]	64	1		T250	3		T252	2		T311	1
all_values[5]	auto[1]	auto[1]	auto[1]	46	1		T250	1		T251	1		T252	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal