Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	312984	1		T1	1		T2	2		T3	1
all_values[1]	312984	1		T1	1		T2	2		T3	1
all_values[2]	312984	1		T1	1		T2	2		T3	1
all_values[3]	312984	1		T1	1		T2	2		T3	1
all_values[4]	312984	1		T1	1		T2	2		T3	1
all_values[5]	312984	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	632417	1		T1	6		T2	12		T3	6
auto[1]	1245487	1		T7	13448		T32	4336		T33	640

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	922301	1		T1	4		T2	6		T3	4
auto[1]	955603	1		T1	2		T2	6		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	312827	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	157	1		T253	7		T254	4		T255	4
all_values[1]	auto[0]	auto[1]	312826	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	158	1		T253	7		T254	1		T255	1
all_values[2]	auto[0]	auto[0]	1627	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	55	1		T253	2		T254	1		T255	2
all_values[2]	auto[1]	auto[0]	311242	1		T7	3362		T32	1084		T33	160
all_values[2]	auto[1]	auto[1]	60	1		T253	1		T254	3		T255	1
all_values[3]	auto[0]	auto[0]	1645	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	64	1		T253	2		T254	2		T255	3
all_values[3]	auto[1]	auto[0]	89949	1		T7	1681		T32	542		T33	79
all_values[3]	auto[1]	auto[1]	221326	1		T7	1681		T32	542		T33	81
all_values[4]	auto[0]	auto[0]	1140	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	538	1		T2	1		T5	1		T12	1
all_values[4]	auto[1]	auto[0]	203875	1		T7	1681		T32	542		T33	79
all_values[4]	auto[1]	auto[1]	107431	1		T7	1681		T32	542		T33	81
all_values[5]	auto[0]	auto[0]	1601	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	94	1		T2	1		T43	1		T44	1
all_values[5]	auto[1]	auto[0]	311222	1		T7	3362		T32	1084		T33	160
all_values[5]	auto[1]	auto[1]	67	1		T253	1		T254	3		T326	1