Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	236545	1		T2	626		T3	1		T17	1
auto[FlashEraseBank]	268797	1		T2	644		T7	821		T18	3

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	253764	1		T2	549		T7	1681		T5	200
auto[FlashOpProgram]	232545	1		T2	721		T3	1		T17	1
auto[FlashOpErase]	15033	1		T5	100		T12	2		T18	4
auto[FlashOpInvalid]	4000	1		T5	200		T29	200		T50	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	253764	1		T2	549		T7	1681		T5	200
op[FlashOpProgram]	232545	1		T2	721		T3	1		T17	1
op[FlashOpErase]	15033	1		T5	100		T12	2		T18	4
read_erase_read	557	1		T79	1		T36	17		T40	3
read_prog_read	789	1		T2	5		T18	1		T6	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	368850	1		T2	1097		T7	1681		T5	588
auto[FlashPartInfo]	132814	1		T2	168		T3	1		T17	1
auto[FlashPartInfo1]	840	1		T2	1		T5	6		T61	5
auto[FlashPartInfo2]	2838	1		T2	4		T30	4		T61	16

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	185896	1		T2	437		T7	1681		T5	196
auto[FlashPartData]	auto[FlashOpProgram]	175423	1		T2	660		T5	98		T18	5
auto[FlashPartData]	auto[FlashOpErase]	3601	1		T5	98		T12	1		T18	4
auto[FlashPartData]	auto[FlashOpInvalid]	3930	1		T5	196		T29	196		T50	196
auto[FlashPartInfo]	auto[FlashOpRead]	65358	1		T2	107		T5	2		T60	1
auto[FlashPartInfo]	auto[FlashOpProgram]	55999	1		T2	61		T3	1		T17	1
auto[FlashPartInfo]	auto[FlashOpErase]	11397	1		T5	1		T12	1		T62	121
auto[FlashPartInfo]	auto[FlashOpInvalid]	60	1		T5	2		T29	4		T50	2
auto[FlashPartInfo1]	auto[FlashOpRead]	663	1		T2	1		T5	2		T61	5
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T5	1		T78	32		T50	1
auto[FlashPartInfo1]	auto[FlashOpErase]	7	1		T5	1		T50	1		T137	2
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T5	2		T50	2		T426	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1847	1		T2	4		T30	3		T61	7
auto[FlashPartInfo2]	auto[FlashOpProgram]	959	1		T30	1		T61	9		T48	7
auto[FlashPartInfo2]	auto[FlashOpErase]	28	1		T24	1		T342	2		T207	3
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T427	2		T428	2		-	-