Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg
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Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.62 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 1 31 96.88


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
evic_cfg_cp 4 0 4 100.00 100 1 1 4
evic_idx_cp 4 0 4 100.00 100 1 1 0
evic_op_cp 2 0 2 100.00 100 1 1 0


Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
evic_all_cross 32 1 31 96.88 100 1 1 0


Summary for Variable evic_cfg_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for evic_cfg_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29568 1 T5 400 T30 1 T62 252
auto[1] 47 1 T36 4 T342 8 T343 1
auto[2] 66 1 T30 1 T36 7 T25 4
auto[3] 206 1 T203 1 T207 6 T344 1



Summary for Variable evic_idx_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for evic_idx_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
evic_idx[0] 7469 1 T5 100 T62 63 T29 100
evic_idx[1] 7473 1 T5 100 T62 63 T29 100
evic_idx[2] 7474 1 T5 100 T62 63 T29 100
evic_idx[3] 7471 1 T5 100 T30 2 T62 63



Summary for Variable evic_op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for evic_op_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
evic_op[1] 28968 1 T5 400 T62 252 T29 400
evic_op[2] 311 1 T30 2 T50 4 T40 4



Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 1 31 96.88 1


Automatically Generated Cross Bins for evic_all_cross

Uncovered bins
evic_idx_cpevic_op_cpevic_cfg_cpCOUNTAT LEASTNUMBER
[evic_idx[0]] [evic_op[2]] [auto[1]] 0 1 1


Covered bins
evic_idx_cpevic_op_cpevic_cfg_cpCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
evic_idx[0] evic_op[1] auto[0] 7182 1 T5 100 T62 63 T29 100
evic_idx[0] evic_op[1] auto[1] 11 1 T36 1 T342 3 T345 1
evic_idx[0] evic_op[1] auto[2] 9 1 T36 1 T207 2 T323 3
evic_idx[0] evic_op[1] auto[3] 40 1 T207 1 T323 4 T346 1
evic_idx[0] evic_op[2] auto[0] 63 1 T50 1 T40 1 T70 4
evic_idx[0] evic_op[2] auto[2] 5 1 T45 1 T208 2 T347 1
evic_idx[0] evic_op[2] auto[3] 7 1 T344 1 T348 1 T349 1
evic_idx[1] evic_op[1] auto[0] 7182 1 T5 100 T62 63 T29 100
evic_idx[1] evic_op[1] auto[1] 7 1 T36 1 T342 2 T350 1
evic_idx[1] evic_op[1] auto[2] 8 1 T36 2 T323 2 T345 1
evic_idx[1] evic_op[1] auto[3] 47 1 T207 2 T323 2 T346 1
evic_idx[1] evic_op[2] auto[0] 60 1 T50 1 T40 1 T70 4
evic_idx[1] evic_op[2] auto[1] 2 1 T343 1 T351 1 - -
evic_idx[1] evic_op[2] auto[2] 3 1 T352 1 T353 1 T354 1
evic_idx[1] evic_op[2] auto[3] 12 1 T355 1 T356 1 T276 1
evic_idx[2] evic_op[1] auto[0] 7181 1 T5 100 T62 63 T29 100
evic_idx[2] evic_op[1] auto[1] 8 1 T36 1 T342 1 T345 1
evic_idx[2] evic_op[1] auto[2] 10 1 T36 3 T323 3 T357 1
evic_idx[2] evic_op[1] auto[3] 42 1 T207 2 T323 2 T346 2
evic_idx[2] evic_op[2] auto[0] 62 1 T50 1 T40 1 T45 1
evic_idx[2] evic_op[2] auto[1] 4 1 T358 1 T359 2 T351 1
evic_idx[2] evic_op[2] auto[2] 4 1 T360 1 T352 2 T354 1
evic_idx[2] evic_op[2] auto[3] 11 1 T203 1 T275 1 T360 1
evic_idx[3] evic_op[1] auto[0] 7181 1 T5 100 T62 63 T29 100
evic_idx[3] evic_op[1] auto[1] 11 1 T36 1 T342 2 T345 1
evic_idx[3] evic_op[1] auto[2] 10 1 T36 1 T207 2 T323 3
evic_idx[3] evic_op[1] auto[3] 39 1 T207 1 T323 3 T346 1
evic_idx[3] evic_op[2] auto[0] 65 1 T30 1 T50 1 T40 1
evic_idx[3] evic_op[2] auto[1] 4 1 T361 1 T362 1 T109 1
evic_idx[3] evic_op[2] auto[2] 1 1 T30 1 - - - -
evic_idx[3] evic_op[2] auto[3] 8 1 T363 1 T364 1 T365 1

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