Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
5128 | 
1 | 
 | 
T54 | 
149 | 
 | 
T55 | 
221 | 
 | 
T56 | 
104 | 
| instr_types[0] | 
6015 | 
1 | 
 | 
T54 | 
163 | 
 | 
T55 | 
254 | 
 | 
T56 | 
325 | 
| instr_types[1] | 
4066536 | 
1 | 
 | 
T2 | 
16550 | 
 | 
T4 | 
16649 | 
 | 
T7 | 
16679 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4075669 | 
1 | 
 | 
T2 | 
16550 | 
 | 
T4 | 
16649 | 
 | 
T7 | 
16679 | 
| auto[1] | 
2010 | 
1 | 
 | 
T54 | 
186 | 
 | 
T55 | 
190 | 
 | 
T56 | 
203 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
4641 | 
1 | 
 | 
T54 | 
86 | 
 | 
T55 | 
166 | 
 | 
T56 | 
89 | 
| auto[0] | 
instr_types[0] | 
5178 | 
1 | 
 | 
T54 | 
118 | 
 | 
T55 | 
185 | 
 | 
T56 | 
198 | 
| auto[0] | 
instr_types[1] | 
4065850 | 
1 | 
 | 
T2 | 
16550 | 
 | 
T4 | 
16649 | 
 | 
T7 | 
16679 | 
| auto[1] | 
others | 
487 | 
1 | 
 | 
T54 | 
63 | 
 | 
T55 | 
55 | 
 | 
T56 | 
15 | 
| auto[1] | 
instr_types[0] | 
837 | 
1 | 
 | 
T54 | 
45 | 
 | 
T55 | 
69 | 
 | 
T56 | 
127 | 
| auto[1] | 
instr_types[1] | 
686 | 
1 | 
 | 
T54 | 
78 | 
 | 
T55 | 
66 | 
 | 
T56 | 
61 |