Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	17850	1		T329	15631		T330	2219		-	-
rd_lvl[2]	23830	1		T331	2803		T188	1346		T332	2255
rd_lvl[3]	17022	1		T225	969		T331	1869		T188	641
rd_lvl[4]	38182	1		T268	5373		T225	938		T333	3096
rd_lvl[5]	19892	1		T21	859		T268	855		T225	70
rd_lvl[6]	28267	1		T21	1159		T222	2277		T225	109
rd_lvl[7]	10601	1		T21	412		T243	1786		T222	320
rd_lvl[8]	6125	1		T21	42		T243	1458		T225	26
rd_lvl[9]	2452	1		T209	173		T332	32		T334	351
rd_lvl[10]	8077	1		T7	1372		T209	25		T188	2
rd_lvl[11]	2294	1		T7	309		T21	42		T114	692
rd_lvl[12]	5752	1		T209	46		T335	1276		T188	86
rd_lvl[13]	4148	1		T32	315		T225	75		T335	400
rd_lvl[14]	5999	1		T32	224		T336	1496		T337	739
rd_lvl[15]	4562	1		T33	56		T42	196		T274	633