Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	312984	1		T1	1		T2	2		T3	1
all_pins[1]	312984	1		T1	1		T2	2		T3	1
all_pins[2]	312984	1		T1	1		T2	2		T3	1
all_pins[3]	312984	1		T1	1		T2	2		T3	1
all_pins[4]	312984	1		T1	1		T2	2		T3	1
all_pins[5]	312984	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1554949	1		T1	6		T2	12		T3	6
values[0x1]	322955	1		T7	3362		T32	1084		T33	210
transitions[0x0=>0x1]	290942	1		T7	3362		T32	1084		T33	160
transitions[0x1=>0x0]	290929	1		T7	3362		T32	1084		T33	160

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	312827	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	157	1		T253	7		T254	4		T255	4
all_pins[0]	transitions[0x0=>0x1]	69	1		T254	3		T255	3		T324	1
all_pins[0]	transitions[0x1=>0x0]	70	1		T326	3		T324	3		T325	3
all_pins[1]	values[0x0]	312826	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	158	1		T253	7		T254	1		T255	1
all_pins[1]	transitions[0x0=>0x1]	133	1		T253	6		T254	1		T255	1
all_pins[1]	transitions[0x1=>0x0]	4879	1		T33	25		T42	1147		T274	1056
all_pins[2]	values[0x0]	308080	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	4904	1		T33	25		T42	1147		T274	1056
all_pins[2]	transitions[0x0=>0x1]	47	1		T253	1		T254	2		T255	1
all_pins[2]	transitions[0x1=>0x0]	195437	1		T7	1681		T32	542		T33	56
all_pins[3]	values[0x0]	112690	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	200294	1		T7	1681		T32	542		T33	81
all_pins[3]	transitions[0x0=>0x1]	173308	1		T7	1681		T32	542		T33	56
all_pins[3]	transitions[0x1=>0x0]	90389	1		T7	1681		T32	542		T33	79
all_pins[4]	values[0x0]	195609	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	117375	1		T7	1681		T32	542		T33	104
all_pins[4]	transitions[0x0=>0x1]	117358	1		T7	1681		T32	542		T33	104
all_pins[4]	transitions[0x1=>0x0]	50	1		T254	2		T326	1		T325	2
all_pins[5]	values[0x0]	312917	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	67	1		T253	1		T254	3		T326	1
all_pins[5]	transitions[0x0=>0x1]	27	1		T324	2		T325	1		T366	1
all_pins[5]	transitions[0x1=>0x0]	104	1		T253	5		T254	2		T255	4