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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.00 95.23 93.81 98.31 92.52 97.12 96.89 98.15


Total test records in report: 1276
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T1077 /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.927955727 Aug 05 07:29:01 PM PDT 24 Aug 05 07:29:45 PM PDT 24 3940315800 ps
T409 /workspace/coverage/default/7.flash_ctrl_sec_info_access.3533791518 Aug 05 07:20:37 PM PDT 24 Aug 05 07:21:43 PM PDT 24 7029834300 ps
T1078 /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.3749749462 Aug 05 07:30:38 PM PDT 24 Aug 05 07:32:37 PM PDT 24 12798818800 ps
T1079 /workspace/coverage/default/36.flash_ctrl_rw_evict.2470083344 Aug 05 07:29:11 PM PDT 24 Aug 05 07:29:40 PM PDT 24 177829900 ps
T1080 /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.842765150 Aug 05 07:28:14 PM PDT 24 Aug 05 07:29:12 PM PDT 24 1710203900 ps
T1081 /workspace/coverage/default/4.flash_ctrl_erase_suspend.582039351 Aug 05 07:17:54 PM PDT 24 Aug 05 07:24:30 PM PDT 24 10761559500 ps
T1082 /workspace/coverage/default/35.flash_ctrl_otp_reset.2047435146 Aug 05 07:29:02 PM PDT 24 Aug 05 07:31:13 PM PDT 24 70577300 ps
T1083 /workspace/coverage/default/0.flash_ctrl_otp_reset.1529129060 Aug 05 07:11:41 PM PDT 24 Aug 05 07:13:52 PM PDT 24 132960200 ps
T1084 /workspace/coverage/default/6.flash_ctrl_intr_rd.1855735849 Aug 05 07:20:28 PM PDT 24 Aug 05 07:23:38 PM PDT 24 6223781700 ps
T1085 /workspace/coverage/default/40.flash_ctrl_disable.449067450 Aug 05 07:29:44 PM PDT 24 Aug 05 07:30:06 PM PDT 24 28568300 ps
T1086 /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.4031448375 Aug 05 07:25:24 PM PDT 24 Aug 05 07:25:54 PM PDT 24 40639500 ps
T1087 /workspace/coverage/default/15.flash_ctrl_disable.4158011126 Aug 05 07:25:25 PM PDT 24 Aug 05 07:25:47 PM PDT 24 27300700 ps
T1088 /workspace/coverage/default/7.flash_ctrl_prog_reset.1576655808 Aug 05 07:20:38 PM PDT 24 Aug 05 07:20:52 PM PDT 24 74231000 ps
T1089 /workspace/coverage/default/7.flash_ctrl_intr_wr.3443117869 Aug 05 07:20:41 PM PDT 24 Aug 05 07:21:47 PM PDT 24 2131919900 ps
T1090 /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.2847683016 Aug 05 07:14:30 PM PDT 24 Aug 05 07:14:44 PM PDT 24 24723500 ps
T1091 /workspace/coverage/default/7.flash_ctrl_error_mp.311558616 Aug 05 07:20:27 PM PDT 24 Aug 05 08:03:10 PM PDT 24 41529152700 ps
T1092 /workspace/coverage/default/0.flash_ctrl_disable.716078744 Aug 05 07:12:28 PM PDT 24 Aug 05 07:12:49 PM PDT 24 10310000 ps
T1093 /workspace/coverage/default/27.flash_ctrl_prog_reset.1580741684 Aug 05 07:27:51 PM PDT 24 Aug 05 07:30:45 PM PDT 24 19145146000 ps
T1094 /workspace/coverage/default/3.flash_ctrl_oversize_error.1040311797 Aug 05 07:17:08 PM PDT 24 Aug 05 07:20:25 PM PDT 24 17488412000 ps
T1095 /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.2248413959 Aug 05 07:24:00 PM PDT 24 Aug 05 07:24:32 PM PDT 24 29875200 ps
T1096 /workspace/coverage/default/19.flash_ctrl_otp_reset.2475126884 Aug 05 07:26:31 PM PDT 24 Aug 05 07:28:44 PM PDT 24 140977100 ps
T1097 /workspace/coverage/default/13.flash_ctrl_disable.3735026631 Aug 05 07:24:02 PM PDT 24 Aug 05 07:24:25 PM PDT 24 67639300 ps
T1098 /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.3640155145 Aug 05 07:11:41 PM PDT 24 Aug 05 07:54:18 PM PDT 24 279029203100 ps
T1099 /workspace/coverage/default/11.flash_ctrl_smoke.518845591 Aug 05 07:22:43 PM PDT 24 Aug 05 07:24:59 PM PDT 24 1633743600 ps
T1100 /workspace/coverage/default/30.flash_ctrl_connect.2079063017 Aug 05 07:28:33 PM PDT 24 Aug 05 07:28:49 PM PDT 24 22631200 ps
T1101 /workspace/coverage/default/43.flash_ctrl_otp_reset.2391644688 Aug 05 07:30:02 PM PDT 24 Aug 05 07:32:14 PM PDT 24 51213400 ps
T1102 /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.1332887882 Aug 05 07:22:25 PM PDT 24 Aug 05 07:26:28 PM PDT 24 12208648500 ps
T1103 /workspace/coverage/default/32.flash_ctrl_sec_info_access.2022973364 Aug 05 07:28:40 PM PDT 24 Aug 05 07:29:55 PM PDT 24 17694582300 ps
T1104 /workspace/coverage/default/45.flash_ctrl_alert_test.2257789648 Aug 05 07:30:39 PM PDT 24 Aug 05 07:30:52 PM PDT 24 36434700 ps
T1105 /workspace/coverage/default/1.flash_ctrl_re_evict.2485810662 Aug 05 07:14:11 PM PDT 24 Aug 05 07:14:43 PM PDT 24 89156500 ps
T1106 /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1678099200 Aug 05 07:29:01 PM PDT 24 Aug 05 07:31:16 PM PDT 24 4892658100 ps
T1107 /workspace/coverage/default/12.flash_ctrl_prog_reset.113990799 Aug 05 07:23:34 PM PDT 24 Aug 05 07:23:48 PM PDT 24 67884300 ps
T163 /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.3003552632 Aug 05 07:16:11 PM PDT 24 Aug 05 07:29:43 PM PDT 24 40122678800 ps
T1108 /workspace/coverage/default/79.flash_ctrl_connect.1167336591 Aug 05 07:31:23 PM PDT 24 Aug 05 07:31:39 PM PDT 24 14426400 ps
T1109 /workspace/coverage/default/21.flash_ctrl_smoke.1160615097 Aug 05 07:26:45 PM PDT 24 Aug 05 07:29:11 PM PDT 24 85059700 ps
T354 /workspace/coverage/default/14.flash_ctrl_rw_evict.4093527025 Aug 05 07:24:27 PM PDT 24 Aug 05 07:24:56 PM PDT 24 98808000 ps
T1110 /workspace/coverage/default/33.flash_ctrl_connect.538844195 Aug 05 07:28:52 PM PDT 24 Aug 05 07:29:05 PM PDT 24 32053000 ps
T1111 /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1185147928 Aug 05 07:26:16 PM PDT 24 Aug 05 07:27:05 PM PDT 24 10033508700 ps
T1112 /workspace/coverage/default/12.flash_ctrl_rw_evict.1202881472 Aug 05 07:23:35 PM PDT 24 Aug 05 07:24:04 PM PDT 24 30447600 ps
T1113 /workspace/coverage/default/42.flash_ctrl_connect.3354289629 Aug 05 07:30:02 PM PDT 24 Aug 05 07:30:15 PM PDT 24 33204400 ps
T1114 /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.3253060866 Aug 05 07:23:23 PM PDT 24 Aug 05 07:38:06 PM PDT 24 270239667400 ps
T1115 /workspace/coverage/default/7.flash_ctrl_re_evict.1350159169 Aug 05 07:20:37 PM PDT 24 Aug 05 07:21:13 PM PDT 24 76491200 ps
T1116 /workspace/coverage/default/10.flash_ctrl_otp_reset.3923051494 Aug 05 07:22:25 PM PDT 24 Aug 05 07:24:17 PM PDT 24 181833900 ps
T1117 /workspace/coverage/default/5.flash_ctrl_rw_evict.4034300259 Aug 05 07:19:11 PM PDT 24 Aug 05 07:19:43 PM PDT 24 63981700 ps
T1118 /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.3931930870 Aug 05 07:26:01 PM PDT 24 Aug 05 07:26:15 PM PDT 24 48201800 ps
T1119 /workspace/coverage/default/25.flash_ctrl_sec_info_access.494551971 Aug 05 07:27:39 PM PDT 24 Aug 05 07:28:48 PM PDT 24 6492074300 ps
T1120 /workspace/coverage/default/58.flash_ctrl_connect.1242804375 Aug 05 07:31:00 PM PDT 24 Aug 05 07:31:16 PM PDT 24 14778400 ps
T1121 /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2366091603 Aug 05 07:21:34 PM PDT 24 Aug 05 07:23:46 PM PDT 24 10012261500 ps
T1122 /workspace/coverage/default/1.flash_ctrl_host_dir_rd.2140636912 Aug 05 07:13:19 PM PDT 24 Aug 05 07:15:02 PM PDT 24 59016500 ps
T1123 /workspace/coverage/default/14.flash_ctrl_mp_regions.2658383125 Aug 05 07:24:16 PM PDT 24 Aug 05 07:32:28 PM PDT 24 29278396700 ps
T1124 /workspace/coverage/default/13.flash_ctrl_rw_evict.1555530939 Aug 05 07:24:01 PM PDT 24 Aug 05 07:24:32 PM PDT 24 32890100 ps
T1125 /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.394060123 Aug 05 07:18:28 PM PDT 24 Aug 05 07:22:29 PM PDT 24 75405940100 ps
T1126 /workspace/coverage/default/47.flash_ctrl_sec_info_access.1154771047 Aug 05 07:30:38 PM PDT 24 Aug 05 07:32:11 PM PDT 24 15662178900 ps
T1127 /workspace/coverage/default/73.flash_ctrl_otp_reset.2133802626 Aug 05 07:31:03 PM PDT 24 Aug 05 07:33:16 PM PDT 24 38210500 ps
T1128 /workspace/coverage/default/0.flash_ctrl_read_word_sweep.1694201922 Aug 05 07:11:55 PM PDT 24 Aug 05 07:12:10 PM PDT 24 174759500 ps
T1129 /workspace/coverage/default/8.flash_ctrl_prog_reset.233761768 Aug 05 07:21:36 PM PDT 24 Aug 05 07:21:50 PM PDT 24 69779500 ps
T351 /workspace/coverage/default/3.flash_ctrl_fs_sup.424429565 Aug 05 07:17:29 PM PDT 24 Aug 05 07:18:10 PM PDT 24 522393600 ps
T1130 /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.301958519 Aug 05 07:20:27 PM PDT 24 Aug 05 07:21:47 PM PDT 24 10020736400 ps
T1131 /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.2516373424 Aug 05 07:17:35 PM PDT 24 Aug 05 07:17:48 PM PDT 24 46549100 ps
T1132 /workspace/coverage/default/1.flash_ctrl_config_regwen.315417069 Aug 05 07:14:28 PM PDT 24 Aug 05 07:14:42 PM PDT 24 39008600 ps
T1133 /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2373118127 Aug 05 07:25:45 PM PDT 24 Aug 05 07:26:57 PM PDT 24 10023151700 ps
T73 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1303026458 Aug 05 06:31:12 PM PDT 24 Aug 05 06:31:29 PM PDT 24 418055300 ps
T74 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3803496124 Aug 05 06:30:54 PM PDT 24 Aug 05 06:31:30 PM PDT 24 881664500 ps
T253 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3530959760 Aug 05 06:31:17 PM PDT 24 Aug 05 06:31:31 PM PDT 24 32313700 ps
T123 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.174948819 Aug 05 06:30:40 PM PDT 24 Aug 05 06:30:59 PM PDT 24 53951100 ps
T1134 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3624565823 Aug 05 06:30:45 PM PDT 24 Aug 05 06:31:00 PM PDT 24 17498100 ps
T75 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1181826507 Aug 05 06:30:52 PM PDT 24 Aug 05 06:45:47 PM PDT 24 2108199300 ps
T237 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3381743664 Aug 05 06:30:59 PM PDT 24 Aug 05 06:31:34 PM PDT 24 318824300 ps
T254 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.861731006 Aug 05 06:31:03 PM PDT 24 Aug 05 06:31:17 PM PDT 24 25446700 ps
T255 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.781607165 Aug 05 06:31:17 PM PDT 24 Aug 05 06:31:30 PM PDT 24 80443800 ps
T1135 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3602981620 Aug 05 06:30:57 PM PDT 24 Aug 05 06:31:13 PM PDT 24 43826300 ps
T126 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1617819371 Aug 05 06:31:02 PM PDT 24 Aug 05 06:31:22 PM PDT 24 982203100 ps
T326 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2593402031 Aug 05 06:30:54 PM PDT 24 Aug 05 06:31:07 PM PDT 24 18458900 ps
T127 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4224514876 Aug 05 06:31:03 PM PDT 24 Aug 05 06:31:19 PM PDT 24 164989400 ps
T324 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.435537283 Aug 05 06:31:16 PM PDT 24 Aug 05 06:31:30 PM PDT 24 25356600 ps
T212 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2689437985 Aug 05 06:30:58 PM PDT 24 Aug 05 06:31:17 PM PDT 24 116133900 ps
T1136 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1393620442 Aug 05 06:31:12 PM PDT 24 Aug 05 06:31:28 PM PDT 24 11902400 ps
T325 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2007179822 Aug 05 06:31:15 PM PDT 24 Aug 05 06:31:29 PM PDT 24 43328300 ps
T1137 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.926980586 Aug 05 06:30:53 PM PDT 24 Aug 05 06:31:07 PM PDT 24 70692700 ps
T124 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3218112297 Aug 05 06:30:52 PM PDT 24 Aug 05 06:31:12 PM PDT 24 400872400 ps
T238 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1808053714 Aug 05 06:31:13 PM PDT 24 Aug 05 06:31:28 PM PDT 24 77103000 ps
T327 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.870386923 Aug 05 06:30:47 PM PDT 24 Aug 05 06:31:01 PM PDT 24 56754000 ps
T232 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3160604372 Aug 05 06:30:42 PM PDT 24 Aug 05 06:30:55 PM PDT 24 26458400 ps
T1138 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3441235263 Aug 05 06:31:16 PM PDT 24 Aug 05 06:31:29 PM PDT 24 27444700 ps
T125 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3291447726 Aug 05 06:31:10 PM PDT 24 Aug 05 06:31:27 PM PDT 24 88265500 ps
T366 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.482760648 Aug 05 06:31:03 PM PDT 24 Aug 05 06:31:17 PM PDT 24 22592900 ps
T1139 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4215123952 Aug 05 06:31:02 PM PDT 24 Aug 05 06:31:15 PM PDT 24 24077400 ps
T257 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3885899004 Aug 05 06:30:40 PM PDT 24 Aug 05 06:31:06 PM PDT 24 22217000 ps
T248 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1688501231 Aug 05 06:30:48 PM PDT 24 Aug 05 06:31:38 PM PDT 24 3291608100 ps
T227 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1717360120 Aug 05 06:30:50 PM PDT 24 Aug 05 06:31:07 PM PDT 24 49776500 ps
T228 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.138192974 Aug 05 06:30:59 PM PDT 24 Aug 05 06:31:18 PM PDT 24 77962500 ps
T328 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.4109054979 Aug 05 06:31:16 PM PDT 24 Aug 05 06:31:30 PM PDT 24 49018900 ps
T295 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3383921844 Aug 05 06:30:41 PM PDT 24 Aug 05 06:31:26 PM PDT 24 2720728900 ps
T1140 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3449362746 Aug 05 06:31:06 PM PDT 24 Aug 05 06:31:22 PM PDT 24 18404600 ps
T1141 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1411979421 Aug 05 06:31:04 PM PDT 24 Aug 05 06:31:17 PM PDT 24 13182000 ps
T1142 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3908613480 Aug 05 06:30:47 PM PDT 24 Aug 05 06:31:01 PM PDT 24 67939100 ps
T231 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2578069968 Aug 05 06:30:45 PM PDT 24 Aug 05 06:45:57 PM PDT 24 5063764400 ps
T229 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1613703502 Aug 05 06:30:50 PM PDT 24 Aug 05 06:31:06 PM PDT 24 94897600 ps
T1143 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.123354143 Aug 05 06:30:44 PM PDT 24 Aug 05 06:31:25 PM PDT 24 1670219000 ps
T1144 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.4212331833 Aug 05 06:30:43 PM PDT 24 Aug 05 06:30:59 PM PDT 24 17996600 ps
T230 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1760531242 Aug 05 06:30:59 PM PDT 24 Aug 05 06:31:17 PM PDT 24 190023500 ps
T1145 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1928357852 Aug 05 06:31:16 PM PDT 24 Aug 05 06:31:30 PM PDT 24 27270900 ps
T262 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2326451019 Aug 05 06:31:13 PM PDT 24 Aug 05 06:31:30 PM PDT 24 106518900 ps
T1146 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3008521051 Aug 05 06:31:16 PM PDT 24 Aug 05 06:31:30 PM PDT 24 15395500 ps
T239 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1551732652 Aug 05 06:31:00 PM PDT 24 Aug 05 06:31:19 PM PDT 24 57760500 ps
T240 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2812243124 Aug 05 06:30:40 PM PDT 24 Aug 05 06:30:54 PM PDT 24 129157800 ps
T289 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3198865339 Aug 05 06:30:54 PM PDT 24 Aug 05 06:31:13 PM PDT 24 491875100 ps
T1147 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3500944060 Aug 05 06:31:03 PM PDT 24 Aug 05 06:31:18 PM PDT 24 25129300 ps
T241 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3377601657 Aug 05 06:31:03 PM PDT 24 Aug 05 06:31:20 PM PDT 24 142472500 ps
T1148 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3584659397 Aug 05 06:30:58 PM PDT 24 Aug 05 06:31:13 PM PDT 24 43357300 ps
T249 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3924499460 Aug 05 06:30:58 PM PDT 24 Aug 05 06:31:20 PM PDT 24 255896300 ps
T322 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.4258489721 Aug 05 06:31:00 PM PDT 24 Aug 05 06:31:19 PM PDT 24 107388400 ps
T1149 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2726079060 Aug 05 06:30:40 PM PDT 24 Aug 05 06:30:55 PM PDT 24 54717600 ps
T1150 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1169523024 Aug 05 06:31:04 PM PDT 24 Aug 05 06:31:20 PM PDT 24 53044800 ps
T1151 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1384383586 Aug 05 06:30:55 PM PDT 24 Aug 05 06:31:09 PM PDT 24 15967300 ps
T245 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3453953840 Aug 05 06:30:59 PM PDT 24 Aug 05 06:45:44 PM PDT 24 778592100 ps
T242 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1849176591 Aug 05 06:30:57 PM PDT 24 Aug 05 06:31:14 PM PDT 24 93471400 ps
T367 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1480087266 Aug 05 06:30:55 PM PDT 24 Aug 05 06:37:23 PM PDT 24 404740700 ps
T1152 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3780499083 Aug 05 06:31:12 PM PDT 24 Aug 05 06:31:29 PM PDT 24 51026400 ps
T251 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2279255581 Aug 05 06:31:04 PM PDT 24 Aug 05 06:44:01 PM PDT 24 2767647800 ps
T1153 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.4232780514 Aug 05 06:30:42 PM PDT 24 Aug 05 06:30:56 PM PDT 24 16652000 ps
T258 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.715452037 Aug 05 06:30:58 PM PDT 24 Aug 05 06:31:15 PM PDT 24 68177000 ps
T264 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2477419473 Aug 05 06:30:42 PM PDT 24 Aug 05 06:30:58 PM PDT 24 179286700 ps
T263 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2804805657 Aug 05 06:31:03 PM PDT 24 Aug 05 06:31:22 PM PDT 24 81753600 ps
T1154 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1760069128 Aug 05 06:30:43 PM PDT 24 Aug 05 06:31:09 PM PDT 24 35489200 ps
T1155 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2290490812 Aug 05 06:31:10 PM PDT 24 Aug 05 06:31:23 PM PDT 24 86731000 ps
T1156 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3447421429 Aug 05 06:30:52 PM PDT 24 Aug 05 06:31:06 PM PDT 24 44195100 ps
T1157 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3235929490 Aug 05 06:31:15 PM PDT 24 Aug 05 06:31:28 PM PDT 24 67474000 ps
T1158 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1470996862 Aug 05 06:30:42 PM PDT 24 Aug 05 06:31:08 PM PDT 24 28746300 ps
T1159 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2969053166 Aug 05 06:31:18 PM PDT 24 Aug 05 06:31:32 PM PDT 24 19170300 ps
T290 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3872843784 Aug 05 06:30:47 PM PDT 24 Aug 05 06:31:27 PM PDT 24 1560500000 ps
T1160 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2830641376 Aug 05 06:30:45 PM PDT 24 Aug 05 06:31:38 PM PDT 24 422931900 ps
T261 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1426015354 Aug 05 06:30:41 PM PDT 24 Aug 05 06:45:45 PM PDT 24 884494200 ps
T1161 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.5143025 Aug 05 06:30:58 PM PDT 24 Aug 05 06:31:13 PM PDT 24 12465700 ps
T1162 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.871680121 Aug 05 06:30:47 PM PDT 24 Aug 05 06:32:10 PM PDT 24 9562627100 ps
T1163 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.106352199 Aug 05 06:30:59 PM PDT 24 Aug 05 06:31:13 PM PDT 24 103826100 ps
T252 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3902792467 Aug 05 06:30:50 PM PDT 24 Aug 05 06:31:10 PM PDT 24 125280100 ps
T1164 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2467884597 Aug 05 06:31:15 PM PDT 24 Aug 05 06:31:29 PM PDT 24 49537500 ps
T291 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3204544935 Aug 05 06:30:43 PM PDT 24 Aug 05 06:31:00 PM PDT 24 440942500 ps
T1165 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1092032908 Aug 05 06:31:17 PM PDT 24 Aug 05 06:31:31 PM PDT 24 57495300 ps
T371 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.825212220 Aug 05 06:30:59 PM PDT 24 Aug 05 06:45:58 PM PDT 24 355945100 ps
T1166 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.273448907 Aug 05 06:30:43 PM PDT 24 Aug 05 06:30:57 PM PDT 24 92586000 ps
T372 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.105266590 Aug 05 06:30:40 PM PDT 24 Aug 05 06:38:22 PM PDT 24 176669200 ps
T265 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2989925396 Aug 05 06:31:03 PM PDT 24 Aug 05 06:31:23 PM PDT 24 411874900 ps
T1167 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3631388684 Aug 05 06:30:57 PM PDT 24 Aug 05 06:31:15 PM PDT 24 214107800 ps
T292 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1723238051 Aug 05 06:30:45 PM PDT 24 Aug 05 06:31:01 PM PDT 24 100541300 ps
T1168 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1040728916 Aug 05 06:31:13 PM PDT 24 Aug 05 06:31:27 PM PDT 24 15338100 ps
T1169 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.565835236 Aug 05 06:30:55 PM PDT 24 Aug 05 06:31:10 PM PDT 24 17293600 ps
T1170 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1363282759 Aug 05 06:30:41 PM PDT 24 Aug 05 06:30:54 PM PDT 24 59234600 ps
T1171 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1103953750 Aug 05 06:31:09 PM PDT 24 Aug 05 06:31:25 PM PDT 24 40447800 ps
T259 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1519437779 Aug 05 06:31:12 PM PDT 24 Aug 05 06:31:31 PM PDT 24 231939100 ps
T1172 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1929007600 Aug 05 06:30:41 PM PDT 24 Aug 05 06:30:54 PM PDT 24 53210600 ps
T1173 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1799184278 Aug 05 06:30:46 PM PDT 24 Aug 05 06:31:29 PM PDT 24 2288224500 ps
T1174 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.4104782531 Aug 05 06:30:40 PM PDT 24 Aug 05 06:31:15 PM PDT 24 233983800 ps
T1175 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3842546453 Aug 05 06:31:04 PM PDT 24 Aug 05 06:31:20 PM PDT 24 101847400 ps
T1176 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1582862631 Aug 05 06:30:43 PM PDT 24 Aug 05 06:30:57 PM PDT 24 52143800 ps
T1177 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.360111178 Aug 05 06:30:54 PM PDT 24 Aug 05 06:31:10 PM PDT 24 14115100 ps
T1178 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1350594636 Aug 05 06:30:51 PM PDT 24 Aug 05 06:31:08 PM PDT 24 65358600 ps
T1179 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2539676740 Aug 05 06:31:20 PM PDT 24 Aug 05 06:31:34 PM PDT 24 49645100 ps
T1180 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2138019450 Aug 05 06:30:44 PM PDT 24 Aug 05 06:31:01 PM PDT 24 175642000 ps
T233 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2017327174 Aug 05 06:30:40 PM PDT 24 Aug 05 06:30:54 PM PDT 24 32033900 ps
T266 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4037385638 Aug 05 06:30:58 PM PDT 24 Aug 05 06:31:15 PM PDT 24 98466000 ps
T1181 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3885676928 Aug 05 06:31:02 PM PDT 24 Aug 05 06:31:18 PM PDT 24 23063400 ps
T250 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2133269550 Aug 05 06:30:40 PM PDT 24 Aug 05 06:30:58 PM PDT 24 52005700 ps
T293 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.60320711 Aug 05 06:30:58 PM PDT 24 Aug 05 06:31:29 PM PDT 24 830698400 ps
T1182 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.652518213 Aug 05 06:31:13 PM PDT 24 Aug 05 06:31:29 PM PDT 24 130237900 ps
T294 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3036582022 Aug 05 06:31:11 PM PDT 24 Aug 05 06:31:47 PM PDT 24 313566300 ps
T1183 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.4242260908 Aug 05 06:30:40 PM PDT 24 Aug 05 06:31:21 PM PDT 24 1823593700 ps
T1184 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3369041768 Aug 05 06:30:46 PM PDT 24 Aug 05 06:31:00 PM PDT 24 41182900 ps
T1185 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1044661647 Aug 05 06:30:45 PM PDT 24 Aug 05 06:31:03 PM PDT 24 122735600 ps
T260 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1110869108 Aug 05 06:30:41 PM PDT 24 Aug 05 06:31:01 PM PDT 24 62907600 ps
T1186 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3242767614 Aug 05 06:31:18 PM PDT 24 Aug 05 06:31:32 PM PDT 24 17541600 ps
T373 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.921585651 Aug 05 06:31:01 PM PDT 24 Aug 05 06:38:40 PM PDT 24 710788300 ps
T368 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.615769928 Aug 05 06:31:12 PM PDT 24 Aug 05 06:38:56 PM PDT 24 855783900 ps
T1187 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3549244854 Aug 05 06:31:18 PM PDT 24 Aug 05 06:31:32 PM PDT 24 14799000 ps
T1188 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2822113798 Aug 05 06:30:48 PM PDT 24 Aug 05 06:31:33 PM PDT 24 45907600 ps
T1189 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3468637332 Aug 05 06:31:03 PM PDT 24 Aug 05 06:31:17 PM PDT 24 18528700 ps
T1190 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3359905900 Aug 05 06:30:50 PM PDT 24 Aug 05 06:31:03 PM PDT 24 24190400 ps
T1191 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.187970019 Aug 05 06:30:46 PM PDT 24 Aug 05 06:31:01 PM PDT 24 96501000 ps
T1192 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.672454540 Aug 05 06:30:47 PM PDT 24 Aug 05 06:31:06 PM PDT 24 170809600 ps
T1193 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.808535865 Aug 05 06:30:53 PM PDT 24 Aug 05 06:31:07 PM PDT 24 43488900 ps
T1194 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.952832685 Aug 05 06:31:04 PM PDT 24 Aug 05 06:31:22 PM PDT 24 39164200 ps
T1195 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1987253340 Aug 05 06:30:39 PM PDT 24 Aug 05 06:31:13 PM PDT 24 1262403400 ps
T1196 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.500173745 Aug 05 06:30:54 PM PDT 24 Aug 05 06:31:11 PM PDT 24 11672900 ps
T376 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1076265203 Aug 05 06:30:59 PM PDT 24 Aug 05 06:43:41 PM PDT 24 6086167600 ps
T1197 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1792583068 Aug 05 06:30:56 PM PDT 24 Aug 05 06:31:09 PM PDT 24 48476300 ps
T1198 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2150510201 Aug 05 06:31:16 PM PDT 24 Aug 05 06:31:29 PM PDT 24 32950000 ps
T1199 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1461876309 Aug 05 06:31:15 PM PDT 24 Aug 05 06:31:29 PM PDT 24 69435000 ps
T256 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2522302137 Aug 05 06:30:53 PM PDT 24 Aug 05 06:31:13 PM PDT 24 113168300 ps
T1200 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.828129344 Aug 05 06:30:47 PM PDT 24 Aug 05 06:31:02 PM PDT 24 81711500 ps
T267 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3863506759 Aug 05 06:30:51 PM PDT 24 Aug 05 06:31:09 PM PDT 24 182110900 ps
T1201 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.590419486 Aug 05 06:30:58 PM PDT 24 Aug 05 06:31:15 PM PDT 24 224441900 ps
T1202 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1543621158 Aug 05 06:31:03 PM PDT 24 Aug 05 06:31:20 PM PDT 24 82141000 ps
T234 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3132319129 Aug 05 06:30:46 PM PDT 24 Aug 05 06:30:59 PM PDT 24 29157500 ps
T1203 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1972857463 Aug 05 06:31:09 PM PDT 24 Aug 05 06:31:27 PM PDT 24 115944000 ps
T1204 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1043241577 Aug 05 06:31:11 PM PDT 24 Aug 05 06:31:32 PM PDT 24 106473700 ps
T1205 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3650858492 Aug 05 06:31:09 PM PDT 24 Aug 05 06:31:26 PM PDT 24 19755300 ps
T1206 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1023039343 Aug 05 06:31:02 PM PDT 24 Aug 05 06:31:16 PM PDT 24 16977700 ps
T1207 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.74797111 Aug 05 06:31:04 PM PDT 24 Aug 05 06:31:19 PM PDT 24 95473400 ps
T235 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3289584064 Aug 05 06:30:46 PM PDT 24 Aug 05 06:31:00 PM PDT 24 32175400 ps
T1208 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1778720373 Aug 05 06:31:11 PM PDT 24 Aug 05 06:31:31 PM PDT 24 152804200 ps
T1209 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3754776309 Aug 05 06:31:15 PM PDT 24 Aug 05 06:31:28 PM PDT 24 30076000 ps
T1210 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2366028208 Aug 05 06:30:54 PM PDT 24 Aug 05 06:31:09 PM PDT 24 64632400 ps
T1211 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2864982314 Aug 05 06:31:15 PM PDT 24 Aug 05 06:31:29 PM PDT 24 27305500 ps
T236 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2164039490 Aug 05 06:30:42 PM PDT 24 Aug 05 06:30:56 PM PDT 24 17906100 ps
T1212 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1673229913 Aug 05 06:30:44 PM PDT 24 Aug 05 06:31:43 PM PDT 24 1262730700 ps
T1213 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2968551138 Aug 05 06:31:03 PM PDT 24 Aug 05 06:38:53 PM PDT 24 350221700 ps
T1214 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3155912748 Aug 05 06:31:03 PM PDT 24 Aug 05 06:31:23 PM PDT 24 59866900 ps
T1215 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1125433429 Aug 05 06:31:10 PM PDT 24 Aug 05 06:31:31 PM PDT 24 444563200 ps
T1216 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3887527835 Aug 05 06:30:45 PM PDT 24 Aug 05 06:30:59 PM PDT 24 24559200 ps
T1217 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1980175366 Aug 05 06:30:52 PM PDT 24 Aug 05 06:31:27 PM PDT 24 369162200 ps
T1218 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3603796288 Aug 05 06:30:48 PM PDT 24 Aug 05 06:31:07 PM PDT 24 203539700 ps
T1219 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.163466225 Aug 05 06:30:47 PM PDT 24 Aug 05 06:31:07 PM PDT 24 221653000 ps
T1220 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3050838556 Aug 05 06:30:39 PM PDT 24 Aug 05 06:30:53 PM PDT 24 18004800 ps
T1221 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.872654554 Aug 05 06:31:11 PM PDT 24 Aug 05 06:31:27 PM PDT 24 314904800 ps
T1222 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3435632207 Aug 05 06:30:53 PM PDT 24 Aug 05 06:31:14 PM PDT 24 647127700 ps
T1223 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3416420078 Aug 05 06:30:58 PM PDT 24 Aug 05 06:31:14 PM PDT 24 53484200 ps
T1224 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3573187847 Aug 05 06:31:17 PM PDT 24 Aug 05 06:31:30 PM PDT 24 16981700 ps
T1225 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1586679018 Aug 05 06:31:21 PM PDT 24 Aug 05 06:31:34 PM PDT 24 34347400 ps
T1226 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1690399006 Aug 05 06:30:43 PM PDT 24 Aug 05 06:31:00 PM PDT 24 19224600 ps
T1227 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.4142825758 Aug 05 06:31:16 PM PDT 24 Aug 05 06:31:29 PM PDT 24 14321000 ps
T369 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2585264649 Aug 05 06:30:52 PM PDT 24 Aug 05 06:38:30 PM PDT 24 433205200 ps
T1228 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3812736143 Aug 05 06:31:10 PM PDT 24 Aug 05 06:31:44 PM PDT 24 433089000 ps
T1229 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3942423872 Aug 05 06:31:08 PM PDT 24 Aug 05 06:31:27 PM PDT 24 129693700 ps
T1230 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2874203192 Aug 05 06:30:41 PM PDT 24 Aug 05 06:30:55 PM PDT 24 52569700 ps
T1231 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2409378575 Aug 05 06:30:46 PM PDT 24 Aug 05 06:30:59 PM PDT 24 15491000 ps
T1232 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4273772480 Aug 05 06:31:02 PM PDT 24 Aug 05 06:31:18 PM PDT 24 14995600 ps
T1233 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.922824301 Aug 05 06:31:05 PM PDT 24 Aug 05 06:31:20 PM PDT 24 14137500 ps
T1234 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2292129106 Aug 05 06:31:05 PM PDT 24 Aug 05 06:31:23 PM PDT 24 110784800 ps
T1235 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4014743364 Aug 05 06:31:20 PM PDT 24 Aug 05 06:31:33 PM PDT 24 17641500 ps
T1236 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3625454149 Aug 05 06:31:08 PM PDT 24 Aug 05 06:31:24 PM PDT 24 83629200 ps
T1237 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1316431387 Aug 05 06:31:17 PM PDT 24 Aug 05 06:31:31 PM PDT 24 154462300 ps
T374 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2417759996 Aug 05 06:31:09 PM PDT 24 Aug 05 06:37:36 PM PDT 24 857163800 ps
T1238 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1258772818 Aug 05 06:30:47 PM PDT 24 Aug 05 06:31:04 PM PDT 24 21189400 ps
T370 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.493571172 Aug 05 06:31:03 PM PDT 24 Aug 05 06:38:43 PM PDT 24 1465176600 ps
T378 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2773181147 Aug 05 06:30:47 PM PDT 24 Aug 05 06:43:38 PM PDT 24 3301194400 ps
T1239 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.670299278 Aug 05 06:31:06 PM PDT 24 Aug 05 06:31:19 PM PDT 24 14582400 ps
T1240 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3103061859 Aug 05 06:30:59 PM PDT 24 Aug 05 06:31:13 PM PDT 24 15572300 ps
T1241 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1141763393 Aug 05 06:31:20 PM PDT 24 Aug 05 06:31:34 PM PDT 24 25335500 ps
T1242 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.800451006 Aug 05 06:31:01 PM PDT 24 Aug 05 06:31:14 PM PDT 24 23146800 ps
T1243 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1253770571 Aug 05 06:30:51 PM PDT 24 Aug 05 06:31:07 PM PDT 24 24473800 ps
T1244 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1055164993 Aug 05 06:31:10 PM PDT 24 Aug 05 06:31:26 PM PDT 24 13498400 ps
T1245 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3340028451 Aug 05 06:31:10 PM PDT 24 Aug 05 06:37:34 PM PDT 24 722027400 ps
T1246 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1052103933 Aug 05 06:30:52 PM PDT 24 Aug 05 06:31:08 PM PDT 24 76694500 ps
T1247 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.319125182 Aug 05 06:30:42 PM PDT 24 Aug 05 06:31:01 PM PDT 24 215117300 ps
T1248 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1169505045 Aug 05 06:31:17 PM PDT 24 Aug 05 06:31:31 PM PDT 24 14435400 ps
T1249 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1134129097 Aug 05 06:31:16 PM PDT 24 Aug 05 06:31:30 PM PDT 24 17222600 ps
T1250 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.541899162 Aug 05 06:31:07 PM PDT 24 Aug 05 06:31:25 PM PDT 24 325491200 ps
T1251 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.104633187 Aug 05 06:31:10 PM PDT 24 Aug 05 06:31:25 PM PDT 24 43888800 ps
T1252 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1830879773 Aug 05 06:30:59 PM PDT 24 Aug 05 06:31:17 PM PDT 24 434955000 ps
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