Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	239488	1		T1	216		T2	1		T4	1
auto[FlashEraseBank]	268758	1		T4	2		T7	617		T65	20

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	252187	1		T1	17		T4	1		T7	465
auto[FlashOpProgram]	237509	1		T1	192		T2	1		T4	1
auto[FlashOpErase]	14550	1		T1	7		T4	1		T27	18
auto[FlashOpInvalid]	4000	1		T67	200		T151	200		T204	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	252187	1		T1	17		T4	1		T7	465
op[FlashOpProgram]	237509	1		T1	192		T2	1		T4	1
op[FlashOpErase]	14550	1		T1	7		T4	1		T27	18
read_erase_read	559	1		T1	1		T27	18		T6	3
read_prog_read	833	1		T7	3		T26	5		T66	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	370429	1		T2	1		T4	3		T7	1142
auto[FlashPartInfo]	133946	1		T1	216		T7	186		T26	13
auto[FlashPartInfo1]	752	1		T8	2		T68	2		T44	3
auto[FlashPartInfo2]	3119	1		T7	7		T8	2		T68	10

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	182836	1		T4	1		T7	353		T65	20
auto[FlashPartData]	auto[FlashOpProgram]	180012	1		T2	1		T4	1		T7	789
auto[FlashPartData]	auto[FlashOpErase]	3659	1		T4	1		T27	9		T67	98
auto[FlashPartData]	auto[FlashOpInvalid]	3922	1		T67	196		T151	196		T204	198
auto[FlashPartInfo]	auto[FlashOpRead]	66689	1		T1	17		T7	106		T26	10
auto[FlashPartInfo]	auto[FlashOpProgram]	56321	1		T1	192		T7	80		T26	3
auto[FlashPartInfo]	auto[FlashOpErase]	10864	1		T1	7		T27	9		T67	2
auto[FlashPartInfo]	auto[FlashOpInvalid]	72	1		T67	4		T151	4		T204	2
auto[FlashPartInfo1]	auto[FlashOpRead]	586	1		T8	2		T68	2		T44	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T77	1		T104	1		T153	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T79	1		T336	1		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	2076	1		T7	6		T8	2		T68	7
auto[FlashPartInfo2]	auto[FlashOpProgram]	1012	1		T7	1		T68	3		T33	3
auto[FlashPartInfo2]	auto[FlashOpErase]	25	1		T149	2		T159	1		T134	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T159	2		T337	2		T338	2