Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28555	1		T67	400		T28	28		T108	460
auto[1]	36	1		T339	3		T340	5		T341	1
auto[2]	84	1		T26	3		T46	3		T150	1
auto[3]	308	1		T26	1		T27	19		T35	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7253	1		T27	5		T67	100		T28	7
evic_idx[1]	7250	1		T26	1		T27	4		T67	100
evic_idx[2]	7243	1		T26	1		T27	4		T67	100
evic_idx[3]	7237	1		T26	2		T27	6		T67	100

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28079	1		T27	19		T67	400		T108	460
evic_op[2]	308	1		T26	4		T28	28		T30	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[3]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6940	1		T67	100		T108	115		T30	3
evic_idx[0]	evic_op[1]	auto[1]	5	1		T342	1		T343	4		-	-
evic_idx[0]	evic_op[1]	auto[2]	11	1		T344	1		T340	2		T345	3
evic_idx[0]	evic_op[1]	auto[3]	72	1		T27	5		T149	1		T344	1
evic_idx[0]	evic_op[2]	auto[0]	59	1		T28	7		T30	4		T104	2
evic_idx[0]	evic_op[2]	auto[1]	4	1		T339	1		T341	1		T346	1
evic_idx[0]	evic_op[2]	auto[2]	4	1		T46	1		T347	1		T348	1
evic_idx[0]	evic_op[2]	auto[3]	9	1		T349	1		T350	1		T351	1
evic_idx[1]	evic_op[1]	auto[0]	6938	1		T67	100		T108	115		T30	3
evic_idx[1]	evic_op[1]	auto[1]	8	1		T340	2		T342	2		T343	4
evic_idx[1]	evic_op[1]	auto[2]	12	1		T344	1		T352	2		T340	1
evic_idx[1]	evic_op[1]	auto[3]	62	1		T27	4		T149	1		T344	1
evic_idx[1]	evic_op[2]	auto[0]	61	1		T28	7		T30	4		T104	2
evic_idx[1]	evic_op[2]	auto[1]	2	1		T339	1		T353	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	4	1		T26	1		T46	2		T354	1
evic_idx[1]	evic_op[2]	auto[3]	14	1		T35	1		T142	1		T295	1
evic_idx[2]	evic_op[1]	auto[0]	6938	1		T67	100		T108	115		T30	3
evic_idx[2]	evic_op[1]	auto[1]	9	1		T340	2		T342	3		T343	4
evic_idx[2]	evic_op[1]	auto[2]	10	1		T344	2		T340	1		T345	3
evic_idx[2]	evic_op[1]	auto[3]	59	1		T27	4		T149	2		T344	1
evic_idx[2]	evic_op[2]	auto[0]	55	1		T28	7		T30	4		T104	2
evic_idx[2]	evic_op[2]	auto[1]	1	1		T339	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	3	1		T150	1		T355	1		T356	1
evic_idx[2]	evic_op[2]	auto[3]	19	1		T26	1		T47	1		T357	1
evic_idx[3]	evic_op[1]	auto[0]	6940	1		T67	100		T108	115		T30	3
evic_idx[3]	evic_op[1]	auto[1]	7	1		T340	1		T342	1		T343	5
evic_idx[3]	evic_op[1]	auto[2]	7	1		T344	1		T352	1		T345	3
evic_idx[3]	evic_op[1]	auto[3]	61	1		T27	6		T149	2		T266	6
evic_idx[3]	evic_op[2]	auto[0]	56	1		T28	7		T30	4		T104	2
evic_idx[3]	evic_op[2]	auto[2]	5	1		T26	2		T267	1		T355	1
evic_idx[3]	evic_op[2]	auto[3]	12	1		T156	1		T144	1		T46	1