Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
3950 | 
1 | 
 | 
T58 | 
148 | 
 | 
T59 | 
149 | 
 | 
T60 | 
51 | 
| instr_types[0] | 
5442 | 
1 | 
 | 
T58 | 
272 | 
 | 
T59 | 
156 | 
 | 
T60 | 
278 | 
| instr_types[1] | 
4162904 | 
1 | 
 | 
T7 | 
16250 | 
 | 
T26 | 
11 | 
 | 
T27 | 
13 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4170084 | 
1 | 
 | 
T7 | 
16250 | 
 | 
T26 | 
11 | 
 | 
T27 | 
13 | 
| auto[1] | 
2212 | 
1 | 
 | 
T58 | 
226 | 
 | 
T59 | 
122 | 
 | 
T60 | 
175 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
3537 | 
1 | 
 | 
T58 | 
123 | 
 | 
T59 | 
92 | 
 | 
T60 | 
36 | 
| auto[0] | 
instr_types[0] | 
4572 | 
1 | 
 | 
T58 | 
161 | 
 | 
T59 | 
128 | 
 | 
T60 | 
168 | 
| auto[0] | 
instr_types[1] | 
4161975 | 
1 | 
 | 
T7 | 
16250 | 
 | 
T26 | 
11 | 
 | 
T27 | 
13 | 
| auto[1] | 
others | 
413 | 
1 | 
 | 
T58 | 
25 | 
 | 
T59 | 
57 | 
 | 
T60 | 
15 | 
| auto[1] | 
instr_types[0] | 
870 | 
1 | 
 | 
T58 | 
111 | 
 | 
T59 | 
28 | 
 | 
T60 | 
110 | 
| auto[1] | 
instr_types[1] | 
929 | 
1 | 
 | 
T58 | 
90 | 
 | 
T59 | 
37 | 
 | 
T60 | 
50 |