Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	24563	1		T321	15719		T322	8844		-	-
rd_lvl[2]	60291	1		T321	11609		T301	2465		T323	1003
rd_lvl[3]	8564	1		T301	1984		T323	2171		T324	1008
rd_lvl[4]	6282	1		T301	1035		T323	110		T325	1618
rd_lvl[5]	12538	1		T194	495		T301	1665		T323	1613
rd_lvl[6]	15315	1		T9	2485		T265	2742		T194	337
rd_lvl[7]	8323	1		T9	428		T265	365		T194	80
rd_lvl[8]	19450	1		T9	20		T43	3022		T194	38
rd_lvl[9]	6253	1		T42	426		T43	382		T39	115
rd_lvl[10]	4453	1		T42	1107		T326	407		T40	1
rd_lvl[11]	2215	1		T194	39		T39	38		T327	630
rd_lvl[12]	10909	1		T328	1338		T329	337		T327	1119
rd_lvl[13]	4992	1		T328	312		T329	239		T330	1390
rd_lvl[14]	6163	1		T193	1430		T331	1161		T41	1396
rd_lvl[15]	2265	1		T193	263		T332	367		T333	109