Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	309062	1		T1	2		T2	1		T3	1
all_pins[1]	309062	1		T1	2		T2	1		T3	1
all_pins[2]	309062	1		T1	2		T2	1		T3	1
all_pins[3]	309062	1		T1	2		T2	1		T3	1
all_pins[4]	309062	1		T1	2		T2	1		T3	1
all_pins[5]	309062	1		T1	2		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1542708	1		T1	12		T2	6		T3	6
values[0x1]	311664	1		T9	4535		T33	1574		T36	1541
transitions[0x0=>0x1]	278869	1		T9	4535		T33	1574		T36	1541
transitions[0x1=>0x0]	278849	1		T9	4535		T33	1574		T36	1541

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	308907	1		T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	155	1		T248	3		T249	3		T250	4
all_pins[0]	transitions[0x0=>0x1]	88	1		T248	3		T312	1		T314	3
all_pins[0]	transitions[0x1=>0x0]	65	1		T312	1		T316	1		T313	3
all_pins[1]	values[0x0]	308930	1		T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	132	1		T249	3		T250	4		T312	1
all_pins[1]	transitions[0x0=>0x1]	104	1		T249	3		T250	3		T315	4
all_pins[1]	transitions[0x1=>0x0]	3689	1		T333	145		T358	1217		T359	1152
all_pins[2]	values[0x0]	305345	1		T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	3717	1		T333	145		T358	1217		T359	1152
all_pins[2]	transitions[0x0=>0x1]	40	1		T248	2		T249	2		T250	1
all_pins[2]	transitions[0x1=>0x0]	192663	1		T9	2933		T42	1533		T43	3404
all_pins[3]	values[0x0]	112722	1		T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	196340	1		T9	2933		T42	1533		T43	3404
all_pins[3]	transitions[0x0=>0x1]	167366	1		T9	2933		T42	1533		T43	1702
all_pins[3]	transitions[0x1=>0x0]	82279	1		T9	1602		T33	1574		T36	1541
all_pins[4]	values[0x0]	197809	1		T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	111253	1		T9	1602		T33	1574		T36	1541
all_pins[4]	transitions[0x0=>0x1]	111233	1		T9	1602		T33	1574		T36	1541
all_pins[4]	transitions[0x1=>0x0]	47	1		T250	1		T316	2		T313	2
all_pins[5]	values[0x0]	308995	1		T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	67	1		T249	2		T250	1		T316	2
all_pins[5]	transitions[0x0=>0x1]	38	1		T249	1		T313	3		T320	2
all_pins[5]	transitions[0x1=>0x0]	106	1		T248	2		T249	1		T250	3