Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T248	4		T249	4		T250	4
all_values[1]	269	1		T248	4		T249	4		T250	4
all_values[2]	269	1		T248	4		T249	4		T250	4
all_values[3]	269	1		T248	4		T249	4		T250	4
all_values[4]	269	1		T248	4		T249	4		T250	4
all_values[5]	269	1		T248	4		T249	4		T250	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	895	1		T248	17		T249	10		T250	4
auto[1]	719	1		T248	7		T249	14		T250	20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	516	1		T248	10		T249	5		T250	8
auto[1]	1098	1		T248	14		T249	19		T250	16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	948	1		T248	15		T249	16		T250	14
auto[1]	666	1		T248	9		T249	8		T250	10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	85	1		T248	2		T249	2		T312	2
all_values[0]	auto[0]	auto[1]	auto[1]	78	1		T248	2		T249	2		T250	2
all_values[0]	auto[1]	auto[0]	auto[1]	61	1		T312	1		T313	5		T314	1
all_values[0]	auto[1]	auto[1]	auto[1]	45	1		T250	2		T315	2		T314	1
all_values[1]	auto[0]	auto[0]	auto[1]	93	1		T248	1		T249	1		T312	3
all_values[1]	auto[0]	auto[1]	auto[1]	63	1		T249	1		T250	3		T315	2
all_values[1]	auto[1]	auto[0]	auto[1]	68	1		T248	3		T249	1		T312	1
all_values[1]	auto[1]	auto[1]	auto[1]	45	1		T249	1		T250	1		T315	1
all_values[2]	auto[0]	auto[0]	auto[0]	88	1		T248	1		T249	1		T312	2
all_values[2]	auto[0]	auto[1]	auto[0]	66	1		T248	1		T250	3		T315	3
all_values[2]	auto[1]	auto[0]	auto[1]	67	1		T248	1		T249	1		T312	1
all_values[2]	auto[1]	auto[1]	auto[1]	48	1		T248	1		T249	2		T250	1
all_values[3]	auto[0]	auto[0]	auto[0]	73	1		T248	2		T250	1		T312	3
all_values[3]	auto[0]	auto[1]	auto[0]	83	1		T248	1		T249	3		T316	2
all_values[3]	auto[1]	auto[0]	auto[1]	64	1		T250	1		T312	1		T316	1
all_values[3]	auto[1]	auto[1]	auto[1]	49	1		T248	1		T249	1		T250	2
all_values[4]	auto[0]	auto[0]	auto[0]	55	1		T248	1		T312	2		T315	1
all_values[4]	auto[0]	auto[0]	auto[1]	27	1		T249	1		T317	2		T318	1
all_values[4]	auto[0]	auto[1]	auto[0]	39	1		T250	2		T315	2		T313	1
all_values[4]	auto[0]	auto[1]	auto[1]	35	1		T249	2		T250	1		T313	1
all_values[4]	auto[1]	auto[0]	auto[1]	70	1		T248	2		T249	1		T312	1
all_values[4]	auto[1]	auto[1]	auto[1]	43	1		T248	1		T250	1		T312	1
all_values[5]	auto[0]	auto[0]	auto[0]	72	1		T248	4		T249	1		T250	2
all_values[5]	auto[0]	auto[0]	auto[1]	19	1		T315	1		T316	1		T313	1
all_values[5]	auto[0]	auto[1]	auto[0]	40	1		T312	1		T319	1		T318	2
all_values[5]	auto[0]	auto[1]	auto[1]	32	1		T249	2		T313	2		T320	2
all_values[5]	auto[1]	auto[0]	auto[1]	53	1		T249	1		T315	1		T316	2
all_values[5]	auto[1]	auto[1]	auto[1]	53	1		T250	2		T315	1		T316	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal