| T1082 |
/workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.130563569 |
|
|
Aug 06 07:58:19 PM PDT 24 |
Aug 06 07:59:25 PM PDT 24 |
10018312600 ps |
| T1083 |
/workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.512664738 |
|
|
Aug 06 07:59:34 PM PDT 24 |
Aug 06 08:00:05 PM PDT 24 |
134219500 ps |
| T1084 |
/workspace/coverage/default/0.flash_ctrl_connect.233922419 |
|
|
Aug 06 07:55:03 PM PDT 24 |
Aug 06 07:55:19 PM PDT 24 |
37233700 ps |
| T1085 |
/workspace/coverage/default/8.flash_ctrl_hw_sec_otp.3768856185 |
|
|
Aug 06 07:56:35 PM PDT 24 |
Aug 06 07:57:17 PM PDT 24 |
1797883900 ps |
| T1086 |
/workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.1854487265 |
|
|
Aug 06 07:55:09 PM PDT 24 |
Aug 06 08:35:23 PM PDT 24 |
383766301900 ps |
| T1087 |
/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1035589401 |
|
|
Aug 06 07:55:01 PM PDT 24 |
Aug 06 07:56:43 PM PDT 24 |
197097900 ps |
| T1088 |
/workspace/coverage/default/15.flash_ctrl_phy_arb.3202190134 |
|
|
Aug 06 07:57:32 PM PDT 24 |
Aug 06 08:03:11 PM PDT 24 |
2554230600 ps |
| T90 |
/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.1204401982 |
|
|
Aug 06 07:55:58 PM PDT 24 |
Aug 06 07:56:15 PM PDT 24 |
697731700 ps |
| T1089 |
/workspace/coverage/default/9.flash_ctrl_phy_arb.1088206542 |
|
|
Aug 06 07:56:31 PM PDT 24 |
Aug 06 08:04:43 PM PDT 24 |
2060538400 ps |
| T1090 |
/workspace/coverage/default/18.flash_ctrl_invalid_op.1462914852 |
|
|
Aug 06 07:57:54 PM PDT 24 |
Aug 06 07:59:12 PM PDT 24 |
3896720300 ps |
| T1091 |
/workspace/coverage/default/9.flash_ctrl_intr_rd.3711795751 |
|
|
Aug 06 07:56:39 PM PDT 24 |
Aug 06 07:59:43 PM PDT 24 |
7070173100 ps |
| T1092 |
/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.3563177492 |
|
|
Aug 06 07:59:46 PM PDT 24 |
Aug 06 08:02:54 PM PDT 24 |
4761372000 ps |
| T1093 |
/workspace/coverage/default/16.flash_ctrl_disable.4252341434 |
|
|
Aug 06 07:57:44 PM PDT 24 |
Aug 06 07:58:07 PM PDT 24 |
98422100 ps |
| T1094 |
/workspace/coverage/default/50.flash_ctrl_connect.1471881623 |
|
|
Aug 06 08:00:24 PM PDT 24 |
Aug 06 08:00:38 PM PDT 24 |
47659300 ps |
| T1095 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.644397889 |
|
|
Aug 06 07:55:01 PM PDT 24 |
Aug 06 07:55:25 PM PDT 24 |
77191200 ps |
| T1096 |
/workspace/coverage/default/31.flash_ctrl_alert_test.2575282406 |
|
|
Aug 06 07:59:11 PM PDT 24 |
Aug 06 07:59:25 PM PDT 24 |
20874400 ps |
| T1097 |
/workspace/coverage/default/42.flash_ctrl_sec_info_access.1059684438 |
|
|
Aug 06 07:59:47 PM PDT 24 |
Aug 06 08:01:05 PM PDT 24 |
4040035000 ps |
| T1098 |
/workspace/coverage/default/4.flash_ctrl_phy_arb.2185444798 |
|
|
Aug 06 07:55:59 PM PDT 24 |
Aug 06 08:04:34 PM PDT 24 |
4211008000 ps |
| T338 |
/workspace/coverage/default/8.flash_ctrl_invalid_op.1040269405 |
|
|
Aug 06 07:56:31 PM PDT 24 |
Aug 06 07:58:06 PM PDT 24 |
4421654000 ps |
| T124 |
/workspace/coverage/default/3.flash_ctrl_sec_cm.3633808344 |
|
|
Aug 06 07:55:54 PM PDT 24 |
Aug 06 09:19:17 PM PDT 24 |
4629597000 ps |
| T1099 |
/workspace/coverage/default/43.flash_ctrl_sec_info_access.1377551467 |
|
|
Aug 06 08:00:01 PM PDT 24 |
Aug 06 08:01:01 PM PDT 24 |
560847600 ps |
| T1100 |
/workspace/coverage/default/7.flash_ctrl_rw_evict.3643800202 |
|
|
Aug 06 07:56:21 PM PDT 24 |
Aug 06 07:56:53 PM PDT 24 |
50462900 ps |
| T1101 |
/workspace/coverage/default/15.flash_ctrl_hw_rma_reset.2079232826 |
|
|
Aug 06 07:57:34 PM PDT 24 |
Aug 06 08:13:24 PM PDT 24 |
380321402000 ps |
| T16 |
/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.3367503748 |
|
|
Aug 06 07:55:59 PM PDT 24 |
Aug 06 07:56:13 PM PDT 24 |
14936700 ps |
| T1102 |
/workspace/coverage/default/4.flash_ctrl_otp_reset.543892622 |
|
|
Aug 06 07:55:54 PM PDT 24 |
Aug 06 07:57:45 PM PDT 24 |
36443500 ps |
| T1103 |
/workspace/coverage/default/43.flash_ctrl_smoke.3552482023 |
|
|
Aug 06 07:59:44 PM PDT 24 |
Aug 06 08:01:21 PM PDT 24 |
38386500 ps |
| T1104 |
/workspace/coverage/default/7.flash_ctrl_intr_rd.977198880 |
|
|
Aug 06 07:56:35 PM PDT 24 |
Aug 06 08:00:19 PM PDT 24 |
1743281400 ps |
| T1105 |
/workspace/coverage/default/2.flash_ctrl_rd_buff_evict.1135893803 |
|
|
Aug 06 07:55:21 PM PDT 24 |
Aug 06 07:57:03 PM PDT 24 |
818610500 ps |
| T1106 |
/workspace/coverage/default/9.flash_ctrl_otp_reset.2234989874 |
|
|
Aug 06 07:56:31 PM PDT 24 |
Aug 06 07:58:44 PM PDT 24 |
84660700 ps |
| T1107 |
/workspace/coverage/default/42.flash_ctrl_otp_reset.1349654694 |
|
|
Aug 06 07:59:50 PM PDT 24 |
Aug 06 08:02:04 PM PDT 24 |
136410100 ps |
| T336 |
/workspace/coverage/default/4.flash_ctrl_mp_regions.2743950946 |
|
|
Aug 06 07:55:49 PM PDT 24 |
Aug 06 07:59:34 PM PDT 24 |
9646999900 ps |
| T1108 |
/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.2142390433 |
|
|
Aug 06 07:55:53 PM PDT 24 |
Aug 06 08:01:19 PM PDT 24 |
12804448400 ps |
| T1109 |
/workspace/coverage/default/39.flash_ctrl_connect.1297345543 |
|
|
Aug 06 07:59:46 PM PDT 24 |
Aug 06 07:59:59 PM PDT 24 |
80820300 ps |
| T1110 |
/workspace/coverage/default/12.flash_ctrl_alert_test.3264934388 |
|
|
Aug 06 07:57:09 PM PDT 24 |
Aug 06 07:57:23 PM PDT 24 |
36394200 ps |
| T1111 |
/workspace/coverage/default/18.flash_ctrl_ro.777253897 |
|
|
Aug 06 07:57:54 PM PDT 24 |
Aug 06 07:59:55 PM PDT 24 |
4801758300 ps |
| T1112 |
/workspace/coverage/default/17.flash_ctrl_rw_evict.378432886 |
|
|
Aug 06 07:57:46 PM PDT 24 |
Aug 06 07:58:19 PM PDT 24 |
61511800 ps |
| T1113 |
/workspace/coverage/default/15.flash_ctrl_smoke.2210278462 |
|
|
Aug 06 07:57:32 PM PDT 24 |
Aug 06 07:58:24 PM PDT 24 |
135294500 ps |
| T1114 |
/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.4208388036 |
|
|
Aug 06 07:56:31 PM PDT 24 |
Aug 06 07:56:45 PM PDT 24 |
46787900 ps |
| T1115 |
/workspace/coverage/default/79.flash_ctrl_connect.3134209773 |
|
|
Aug 06 08:00:43 PM PDT 24 |
Aug 06 08:00:56 PM PDT 24 |
21949400 ps |
| T1116 |
/workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.550089284 |
|
|
Aug 06 07:57:46 PM PDT 24 |
Aug 06 07:58:17 PM PDT 24 |
30113000 ps |
| T1117 |
/workspace/coverage/default/13.flash_ctrl_wo.3731876233 |
|
|
Aug 06 07:57:07 PM PDT 24 |
Aug 06 08:00:19 PM PDT 24 |
6378494600 ps |
| T1118 |
/workspace/coverage/default/5.flash_ctrl_wo.928482550 |
|
|
Aug 06 07:56:10 PM PDT 24 |
Aug 06 07:57:52 PM PDT 24 |
5170595000 ps |
| T1119 |
/workspace/coverage/default/38.flash_ctrl_smoke.3549463984 |
|
|
Aug 06 07:59:34 PM PDT 24 |
Aug 06 08:01:12 PM PDT 24 |
20897000 ps |
| T1120 |
/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.3658208462 |
|
|
Aug 06 07:55:36 PM PDT 24 |
Aug 06 07:55:50 PM PDT 24 |
26419300 ps |
| T1121 |
/workspace/coverage/default/11.flash_ctrl_ro.646603654 |
|
|
Aug 06 07:56:56 PM PDT 24 |
Aug 06 07:58:55 PM PDT 24 |
5382088600 ps |
| T1122 |
/workspace/coverage/default/27.flash_ctrl_sec_info_access.1418760038 |
|
|
Aug 06 07:58:49 PM PDT 24 |
Aug 06 07:59:43 PM PDT 24 |
435688400 ps |
| T1123 |
/workspace/coverage/default/34.flash_ctrl_smoke.1431012448 |
|
|
Aug 06 07:59:28 PM PDT 24 |
Aug 06 08:01:10 PM PDT 24 |
31061200 ps |
| T1124 |
/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.4219254536 |
|
|
Aug 06 07:56:34 PM PDT 24 |
Aug 06 07:57:30 PM PDT 24 |
10033954800 ps |
| T1125 |
/workspace/coverage/default/2.flash_ctrl_mp_regions.2939431258 |
|
|
Aug 06 07:55:22 PM PDT 24 |
Aug 06 08:02:04 PM PDT 24 |
25898438200 ps |
| T1126 |
/workspace/coverage/default/6.flash_ctrl_hw_rma_reset.2066273918 |
|
|
Aug 06 07:56:19 PM PDT 24 |
Aug 06 08:10:46 PM PDT 24 |
180199081200 ps |
| T1127 |
/workspace/coverage/default/24.flash_ctrl_otp_reset.2422453460 |
|
|
Aug 06 07:58:30 PM PDT 24 |
Aug 06 08:00:43 PM PDT 24 |
128268400 ps |
| T1128 |
/workspace/coverage/default/18.flash_ctrl_wo.4092130074 |
|
|
Aug 06 07:57:55 PM PDT 24 |
Aug 06 08:00:02 PM PDT 24 |
2892000900 ps |
| T1129 |
/workspace/coverage/default/15.flash_ctrl_alert_test.2758327557 |
|
|
Aug 06 07:57:37 PM PDT 24 |
Aug 06 07:57:50 PM PDT 24 |
72042100 ps |
| T1130 |
/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.2310496527 |
|
|
Aug 06 07:55:55 PM PDT 24 |
Aug 06 07:56:24 PM PDT 24 |
30650100 ps |
| T1131 |
/workspace/coverage/default/13.flash_ctrl_ro.1708403231 |
|
|
Aug 06 07:57:08 PM PDT 24 |
Aug 06 07:59:04 PM PDT 24 |
1814125900 ps |
| T1132 |
/workspace/coverage/default/10.flash_ctrl_re_evict.3232438850 |
|
|
Aug 06 07:56:45 PM PDT 24 |
Aug 06 07:57:20 PM PDT 24 |
380923500 ps |
| T1133 |
/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.796548313 |
|
|
Aug 06 07:59:37 PM PDT 24 |
Aug 06 08:00:29 PM PDT 24 |
2133962200 ps |
| T1134 |
/workspace/coverage/default/1.flash_ctrl_host_dir_rd.3044364587 |
|
|
Aug 06 07:55:08 PM PDT 24 |
Aug 06 07:56:06 PM PDT 24 |
207601800 ps |
| T1135 |
/workspace/coverage/default/24.flash_ctrl_smoke.1446916752 |
|
|
Aug 06 07:58:31 PM PDT 24 |
Aug 06 07:59:45 PM PDT 24 |
23318600 ps |
| T1136 |
/workspace/coverage/default/10.flash_ctrl_alert_test.2028795370 |
|
|
Aug 06 07:56:56 PM PDT 24 |
Aug 06 07:57:11 PM PDT 24 |
248854600 ps |
| T1137 |
/workspace/coverage/default/39.flash_ctrl_alert_test.1888752133 |
|
|
Aug 06 07:59:45 PM PDT 24 |
Aug 06 07:59:58 PM PDT 24 |
21714500 ps |
| T230 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2865859987 |
|
|
Aug 06 07:54:28 PM PDT 24 |
Aug 06 07:54:42 PM PDT 24 |
14872900 ps |
| T74 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2552075318 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 08:09:28 PM PDT 24 |
352569000 ps |
| T1138 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.9986517 |
|
|
Aug 06 07:54:53 PM PDT 24 |
Aug 06 07:55:07 PM PDT 24 |
34580400 ps |
| T75 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1969296031 |
|
|
Aug 06 07:54:41 PM PDT 24 |
Aug 06 07:54:58 PM PDT 24 |
68725000 ps |
| T76 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3770119834 |
|
|
Aug 06 07:54:28 PM PDT 24 |
Aug 06 07:54:45 PM PDT 24 |
20666400 ps |
| T1139 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2348553744 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:07 PM PDT 24 |
13550600 ps |
| T118 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3242844255 |
|
|
Aug 06 07:54:38 PM PDT 24 |
Aug 06 07:54:57 PM PDT 24 |
131378400 ps |
| T205 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2174740157 |
|
|
Aug 06 07:54:28 PM PDT 24 |
Aug 06 07:54:47 PM PDT 24 |
91018100 ps |
| T1140 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3793920227 |
|
|
Aug 06 07:54:42 PM PDT 24 |
Aug 06 07:54:58 PM PDT 24 |
14837600 ps |
| T248 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.935484883 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:04 PM PDT 24 |
14054200 ps |
| T235 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2810990953 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:54:55 PM PDT 24 |
111954500 ps |
| T246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.564104929 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:55:03 PM PDT 24 |
530361500 ps |
| T1141 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.248788435 |
|
|
Aug 06 07:54:37 PM PDT 24 |
Aug 06 07:54:53 PM PDT 24 |
12174200 ps |
| T210 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1251334742 |
|
|
Aug 06 07:54:24 PM PDT 24 |
Aug 06 07:54:41 PM PDT 24 |
116077500 ps |
| T249 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3814413293 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:54:40 PM PDT 24 |
15027700 ps |
| T224 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.6634974 |
|
|
Aug 06 07:54:43 PM PDT 24 |
Aug 06 07:55:02 PM PDT 24 |
86190300 ps |
| T206 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3962823617 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 08:02:01 PM PDT 24 |
333913900 ps |
| T250 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3671103798 |
|
|
Aug 06 07:55:01 PM PDT 24 |
Aug 06 07:55:15 PM PDT 24 |
14093800 ps |
| T311 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2651785224 |
|
|
Aug 06 07:54:28 PM PDT 24 |
Aug 06 07:55:08 PM PDT 24 |
2523875500 ps |
| T236 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1052550487 |
|
|
Aug 06 07:54:34 PM PDT 24 |
Aug 06 07:54:55 PM PDT 24 |
332154200 ps |
| T207 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3900812471 |
|
|
Aug 06 07:54:52 PM PDT 24 |
Aug 06 07:55:10 PM PDT 24 |
186685800 ps |
| T312 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.155694352 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:05 PM PDT 24 |
57001600 ps |
| T1142 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.953225824 |
|
|
Aug 06 07:54:50 PM PDT 24 |
Aug 06 07:55:04 PM PDT 24 |
18364200 ps |
| T208 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1268194011 |
|
|
Aug 06 07:54:39 PM PDT 24 |
Aug 06 07:55:00 PM PDT 24 |
447875200 ps |
| T225 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4185768182 |
|
|
Aug 06 07:54:40 PM PDT 24 |
Aug 06 07:55:00 PM PDT 24 |
325475000 ps |
| T237 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.35752512 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:40 PM PDT 24 |
108850700 ps |
| T238 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4207225978 |
|
|
Aug 06 07:54:23 PM PDT 24 |
Aug 06 07:54:53 PM PDT 24 |
161418600 ps |
| T1143 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3775483111 |
|
|
Aug 06 07:54:40 PM PDT 24 |
Aug 06 07:54:53 PM PDT 24 |
34780100 ps |
| T226 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.709756883 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:06 PM PDT 24 |
52712500 ps |
| T1144 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1459565322 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:54:39 PM PDT 24 |
107788100 ps |
| T209 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4285058976 |
|
|
Aug 06 07:54:37 PM PDT 24 |
Aug 06 08:09:38 PM PDT 24 |
392754500 ps |
| T315 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1804903626 |
|
|
Aug 06 07:54:50 PM PDT 24 |
Aug 06 07:55:04 PM PDT 24 |
51309100 ps |
| T1145 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4284121076 |
|
|
Aug 06 07:54:46 PM PDT 24 |
Aug 06 07:55:02 PM PDT 24 |
66267300 ps |
| T316 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.114886820 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:38 PM PDT 24 |
14614400 ps |
| T227 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1460137327 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 08:02:04 PM PDT 24 |
793615100 ps |
| T313 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.657939523 |
|
|
Aug 06 07:54:54 PM PDT 24 |
Aug 06 07:55:07 PM PDT 24 |
21243700 ps |
| T228 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2143747971 |
|
|
Aug 06 07:54:41 PM PDT 24 |
Aug 06 07:54:59 PM PDT 24 |
85838800 ps |
| T229 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1598967213 |
|
|
Aug 06 07:54:38 PM PDT 24 |
Aug 06 07:54:54 PM PDT 24 |
54106100 ps |
| T1146 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3774720555 |
|
|
Aug 06 07:54:54 PM PDT 24 |
Aug 06 07:55:09 PM PDT 24 |
34536700 ps |
| T239 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.689408249 |
|
|
Aug 06 07:54:20 PM PDT 24 |
Aug 06 07:54:54 PM PDT 24 |
581642800 ps |
| T252 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.455000293 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:11 PM PDT 24 |
145440100 ps |
| T231 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3269053707 |
|
|
Aug 06 07:54:16 PM PDT 24 |
Aug 06 07:54:30 PM PDT 24 |
27413000 ps |
| T247 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2898132133 |
|
|
Aug 06 07:54:42 PM PDT 24 |
Aug 06 07:54:58 PM PDT 24 |
68027500 ps |
| T277 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1310804236 |
|
|
Aug 06 07:54:38 PM PDT 24 |
Aug 06 07:54:56 PM PDT 24 |
60222500 ps |
| T1147 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3106875085 |
|
|
Aug 06 07:54:29 PM PDT 24 |
Aug 06 07:54:45 PM PDT 24 |
12978100 ps |
| T278 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4151433227 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 08:01:21 PM PDT 24 |
1703271600 ps |
| T240 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3958199403 |
|
|
Aug 06 07:54:50 PM PDT 24 |
Aug 06 07:55:08 PM PDT 24 |
80411100 ps |
| T314 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2710709644 |
|
|
Aug 06 07:54:52 PM PDT 24 |
Aug 06 07:55:06 PM PDT 24 |
127375500 ps |
| T1148 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.712849034 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:54:42 PM PDT 24 |
21010500 ps |
| T1149 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3379512702 |
|
|
Aug 06 07:54:56 PM PDT 24 |
Aug 06 07:55:14 PM PDT 24 |
208951100 ps |
| T1150 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3712000113 |
|
|
Aug 06 07:54:16 PM PDT 24 |
Aug 06 07:54:32 PM PDT 24 |
92719900 ps |
| T1151 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3575534808 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:54:41 PM PDT 24 |
73494200 ps |
| T279 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3683039556 |
|
|
Aug 06 07:54:47 PM PDT 24 |
Aug 06 07:55:05 PM PDT 24 |
134050300 ps |
| T280 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3351684950 |
|
|
Aug 06 07:54:56 PM PDT 24 |
Aug 06 08:10:16 PM PDT 24 |
1919225100 ps |
| T320 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2636063948 |
|
|
Aug 06 07:54:56 PM PDT 24 |
Aug 06 07:55:10 PM PDT 24 |
17533100 ps |
| T319 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2971701918 |
|
|
Aug 06 07:54:52 PM PDT 24 |
Aug 06 07:55:06 PM PDT 24 |
18962400 ps |
| T1152 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3534741816 |
|
|
Aug 06 07:54:28 PM PDT 24 |
Aug 06 07:54:46 PM PDT 24 |
1562419400 ps |
| T1153 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.233684429 |
|
|
Aug 06 07:55:02 PM PDT 24 |
Aug 06 07:55:16 PM PDT 24 |
16024500 ps |
| T1154 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2262743670 |
|
|
Aug 06 07:54:23 PM PDT 24 |
Aug 06 07:54:49 PM PDT 24 |
49957100 ps |
| T1155 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1393627598 |
|
|
Aug 06 07:54:40 PM PDT 24 |
Aug 06 07:54:54 PM PDT 24 |
27723600 ps |
| T281 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3158286322 |
|
|
Aug 06 07:54:33 PM PDT 24 |
Aug 06 08:09:39 PM PDT 24 |
1720471800 ps |
| T251 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3382568756 |
|
|
Aug 06 07:54:54 PM PDT 24 |
Aug 06 07:55:15 PM PDT 24 |
78498400 ps |
| T1156 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.425330610 |
|
|
Aug 06 07:54:28 PM PDT 24 |
Aug 06 07:54:54 PM PDT 24 |
55567000 ps |
| T1157 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1377518928 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:06 PM PDT 24 |
100310900 ps |
| T232 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1550057276 |
|
|
Aug 06 07:54:36 PM PDT 24 |
Aug 06 07:54:49 PM PDT 24 |
69689000 ps |
| T1158 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.663677601 |
|
|
Aug 06 07:54:33 PM PDT 24 |
Aug 06 07:55:26 PM PDT 24 |
1101007200 ps |
| T317 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.4249474866 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:04 PM PDT 24 |
14857500 ps |
| T282 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.637621031 |
|
|
Aug 06 07:54:41 PM PDT 24 |
Aug 06 07:54:58 PM PDT 24 |
84377000 ps |
| T1159 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3807782196 |
|
|
Aug 06 07:54:39 PM PDT 24 |
Aug 06 07:54:57 PM PDT 24 |
207133200 ps |
| T286 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3491404302 |
|
|
Aug 06 07:54:53 PM PDT 24 |
Aug 06 07:55:11 PM PDT 24 |
113740300 ps |
| T1160 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2004710362 |
|
|
Aug 06 07:55:00 PM PDT 24 |
Aug 06 07:55:14 PM PDT 24 |
55994300 ps |
| T256 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3802330516 |
|
|
Aug 06 07:54:27 PM PDT 24 |
Aug 06 07:54:43 PM PDT 24 |
138799900 ps |
| T1161 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1479680329 |
|
|
Aug 06 07:55:00 PM PDT 24 |
Aug 06 07:55:14 PM PDT 24 |
156677300 ps |
| T1162 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3636423938 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:55:05 PM PDT 24 |
1303387600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4033409928 |
|
|
Aug 06 07:54:27 PM PDT 24 |
Aug 06 07:54:41 PM PDT 24 |
27044100 ps |
| T318 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2159350949 |
|
|
Aug 06 07:54:24 PM PDT 24 |
Aug 06 07:54:38 PM PDT 24 |
57893600 ps |
| T255 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1580354046 |
|
|
Aug 06 07:54:41 PM PDT 24 |
Aug 06 07:54:58 PM PDT 24 |
38863200 ps |
| T1164 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.894714463 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:55:13 PM PDT 24 |
4374043900 ps |
| T1165 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.4002500280 |
|
|
Aug 06 07:54:54 PM PDT 24 |
Aug 06 07:55:07 PM PDT 24 |
39226900 ps |
| T283 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2757049421 |
|
|
Aug 06 07:54:54 PM PDT 24 |
Aug 06 08:02:33 PM PDT 24 |
449573000 ps |
| T1166 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2182524444 |
|
|
Aug 06 07:55:01 PM PDT 24 |
Aug 06 07:55:14 PM PDT 24 |
182517000 ps |
| T253 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.593764753 |
|
|
Aug 06 07:54:40 PM PDT 24 |
Aug 06 07:54:56 PM PDT 24 |
34760500 ps |
| T284 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2681469547 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:55:12 PM PDT 24 |
192426500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3951029725 |
|
|
Aug 06 07:54:52 PM PDT 24 |
Aug 06 07:55:10 PM PDT 24 |
45476100 ps |
| T285 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1033180617 |
|
|
Aug 06 07:54:39 PM PDT 24 |
Aug 06 07:55:14 PM PDT 24 |
201869300 ps |
| T361 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3965552069 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 08:07:19 PM PDT 24 |
793246600 ps |
| T1168 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4276352927 |
|
|
Aug 06 07:54:35 PM PDT 24 |
Aug 06 07:55:09 PM PDT 24 |
118844600 ps |
| T1169 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1382489488 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:06 PM PDT 24 |
326116500 ps |
| T1170 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1450187751 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:40 PM PDT 24 |
34661000 ps |
| T1171 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.234908249 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:07 PM PDT 24 |
12691000 ps |
| T287 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1219155610 |
|
|
Aug 06 07:54:41 PM PDT 24 |
Aug 06 08:09:53 PM PDT 24 |
858512900 ps |
| T1172 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3822532426 |
|
|
Aug 06 07:55:01 PM PDT 24 |
Aug 06 07:55:14 PM PDT 24 |
14847200 ps |
| T1173 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2045599846 |
|
|
Aug 06 07:54:54 PM PDT 24 |
Aug 06 07:55:12 PM PDT 24 |
37254400 ps |
| T288 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1082260942 |
|
|
Aug 06 07:54:53 PM PDT 24 |
Aug 06 08:07:48 PM PDT 24 |
869510900 ps |
| T1174 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3196002323 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:57 PM PDT 24 |
35107000 ps |
| T1175 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1556922389 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:54:41 PM PDT 24 |
14796700 ps |
| T254 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3560226828 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:54:44 PM PDT 24 |
49298600 ps |
| T1176 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2225122898 |
|
|
Aug 06 07:54:24 PM PDT 24 |
Aug 06 07:54:40 PM PDT 24 |
155132000 ps |
| T1177 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2053341589 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:39 PM PDT 24 |
40694400 ps |
| T1178 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2780574139 |
|
|
Aug 06 07:54:42 PM PDT 24 |
Aug 06 07:54:56 PM PDT 24 |
57063600 ps |
| T1179 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1780993768 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:08 PM PDT 24 |
43080000 ps |
| T1180 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3555669012 |
|
|
Aug 06 07:54:39 PM PDT 24 |
Aug 06 07:54:53 PM PDT 24 |
40803800 ps |
| T1181 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.363176992 |
|
|
Aug 06 07:54:36 PM PDT 24 |
Aug 06 07:54:49 PM PDT 24 |
17684000 ps |
| T1182 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3636525755 |
|
|
Aug 06 07:55:01 PM PDT 24 |
Aug 06 07:55:15 PM PDT 24 |
212332800 ps |
| T1183 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1757340499 |
|
|
Aug 06 07:54:37 PM PDT 24 |
Aug 06 07:54:59 PM PDT 24 |
986040100 ps |
| T1184 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3776102043 |
|
|
Aug 06 07:54:49 PM PDT 24 |
Aug 06 07:55:07 PM PDT 24 |
148127000 ps |
| T1185 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.314457599 |
|
|
Aug 06 07:54:53 PM PDT 24 |
Aug 06 07:55:07 PM PDT 24 |
115720700 ps |
| T1186 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3994965298 |
|
|
Aug 06 07:54:34 PM PDT 24 |
Aug 06 07:54:48 PM PDT 24 |
17113300 ps |
| T1187 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1871057945 |
|
|
Aug 06 07:54:52 PM PDT 24 |
Aug 06 07:55:12 PM PDT 24 |
192260800 ps |
| T1188 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3339002998 |
|
|
Aug 06 07:54:28 PM PDT 24 |
Aug 06 07:54:41 PM PDT 24 |
45767800 ps |
| T257 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1108032493 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:42 PM PDT 24 |
43701700 ps |
| T1189 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1626032758 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:07 PM PDT 24 |
13597000 ps |
| T289 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1839181641 |
|
|
Aug 06 07:54:49 PM PDT 24 |
Aug 06 07:55:04 PM PDT 24 |
54120700 ps |
| T1190 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3930162010 |
|
|
Aug 06 07:54:24 PM PDT 24 |
Aug 06 07:54:45 PM PDT 24 |
801585200 ps |
| T1191 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.135031162 |
|
|
Aug 06 07:54:54 PM PDT 24 |
Aug 06 07:55:12 PM PDT 24 |
134004100 ps |
| T1192 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2881674186 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:41 PM PDT 24 |
268607200 ps |
| T363 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2468530558 |
|
|
Aug 06 07:54:17 PM PDT 24 |
Aug 06 08:00:43 PM PDT 24 |
848456400 ps |
| T1193 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1568674572 |
|
|
Aug 06 07:54:37 PM PDT 24 |
Aug 06 07:54:54 PM PDT 24 |
73125500 ps |
| T360 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.4260967608 |
|
|
Aug 06 07:54:41 PM PDT 24 |
Aug 06 08:07:27 PM PDT 24 |
957089600 ps |
| T1194 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2756576255 |
|
|
Aug 06 07:54:42 PM PDT 24 |
Aug 06 07:55:03 PM PDT 24 |
323570800 ps |
| T1195 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1774518219 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:57 PM PDT 24 |
28983400 ps |
| T1196 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2129860105 |
|
|
Aug 06 07:55:00 PM PDT 24 |
Aug 06 07:55:14 PM PDT 24 |
14862200 ps |
| T1197 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1462528119 |
|
|
Aug 06 07:54:55 PM PDT 24 |
Aug 06 07:55:12 PM PDT 24 |
123289900 ps |
| T1198 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.603244689 |
|
|
Aug 06 07:54:49 PM PDT 24 |
Aug 06 07:55:02 PM PDT 24 |
56190200 ps |
| T1199 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3435467337 |
|
|
Aug 06 07:54:38 PM PDT 24 |
Aug 06 07:54:56 PM PDT 24 |
132888400 ps |
| T1200 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2902072242 |
|
|
Aug 06 07:54:38 PM PDT 24 |
Aug 06 07:55:08 PM PDT 24 |
251267100 ps |
| T1201 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1770065173 |
|
|
Aug 06 07:54:47 PM PDT 24 |
Aug 06 07:55:02 PM PDT 24 |
20844700 ps |
| T290 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3176628629 |
|
|
Aug 06 07:54:24 PM PDT 24 |
Aug 06 07:54:39 PM PDT 24 |
226130100 ps |
| T1202 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2838592297 |
|
|
Aug 06 07:54:37 PM PDT 24 |
Aug 06 07:54:51 PM PDT 24 |
28803900 ps |
| T1203 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3556229161 |
|
|
Aug 06 07:54:27 PM PDT 24 |
Aug 06 07:55:26 PM PDT 24 |
659388100 ps |
| T291 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2577033984 |
|
|
Aug 06 07:54:40 PM PDT 24 |
Aug 06 07:55:15 PM PDT 24 |
197687600 ps |
| T1204 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3844429713 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:09 PM PDT 24 |
75239700 ps |
| T1205 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1494616694 |
|
|
Aug 06 07:54:42 PM PDT 24 |
Aug 06 07:55:00 PM PDT 24 |
70510800 ps |
| T1206 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3363325098 |
|
|
Aug 06 07:55:00 PM PDT 24 |
Aug 06 07:55:14 PM PDT 24 |
24269600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.258610041 |
|
|
Aug 06 07:54:39 PM PDT 24 |
Aug 06 07:54:52 PM PDT 24 |
17321000 ps |
| T1208 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3534925542 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:05 PM PDT 24 |
47179400 ps |
| T1209 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1607682663 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:55:03 PM PDT 24 |
643751900 ps |
| T1210 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3056150821 |
|
|
Aug 06 07:54:54 PM PDT 24 |
Aug 06 07:55:07 PM PDT 24 |
39174600 ps |
| T292 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2699682497 |
|
|
Aug 06 07:54:29 PM PDT 24 |
Aug 06 07:54:49 PM PDT 24 |
218984100 ps |
| T1211 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3983608104 |
|
|
Aug 06 07:54:39 PM PDT 24 |
Aug 06 07:54:55 PM PDT 24 |
43503200 ps |
| T1212 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.897994218 |
|
|
Aug 06 07:54:40 PM PDT 24 |
Aug 06 07:54:57 PM PDT 24 |
42492400 ps |
| T258 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2462852814 |
|
|
Aug 06 07:54:49 PM PDT 24 |
Aug 06 08:09:53 PM PDT 24 |
748658100 ps |
| T1213 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3774120778 |
|
|
Aug 06 07:54:45 PM PDT 24 |
Aug 06 07:55:01 PM PDT 24 |
14669000 ps |
| T1214 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2070487357 |
|
|
Aug 06 07:54:37 PM PDT 24 |
Aug 06 07:54:53 PM PDT 24 |
67286700 ps |
| T1215 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.984711113 |
|
|
Aug 06 07:54:36 PM PDT 24 |
Aug 06 07:54:49 PM PDT 24 |
137457100 ps |
| T1216 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.610368166 |
|
|
Aug 06 07:54:39 PM PDT 24 |
Aug 06 07:54:55 PM PDT 24 |
15284000 ps |
| T293 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4141340696 |
|
|
Aug 06 07:54:39 PM PDT 24 |
Aug 06 07:55:01 PM PDT 24 |
874644100 ps |
| T1217 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1961644073 |
|
|
Aug 06 07:55:00 PM PDT 24 |
Aug 06 07:55:13 PM PDT 24 |
15212100 ps |
| T1218 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2842607904 |
|
|
Aug 06 07:54:54 PM PDT 24 |
Aug 06 07:55:11 PM PDT 24 |
357795200 ps |
| T1219 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3605532366 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:05 PM PDT 24 |
30049200 ps |
| T1220 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.564257026 |
|
|
Aug 06 07:54:29 PM PDT 24 |
Aug 06 07:54:45 PM PDT 24 |
146786800 ps |
| T1221 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1205712840 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:40 PM PDT 24 |
204997700 ps |
| T1222 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2055935151 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:05 PM PDT 24 |
35723900 ps |
| T1223 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1307594499 |
|
|
Aug 06 07:54:41 PM PDT 24 |
Aug 06 07:54:54 PM PDT 24 |
42882900 ps |
| T1224 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1071568908 |
|
|
Aug 06 07:54:52 PM PDT 24 |
Aug 06 07:55:09 PM PDT 24 |
66862100 ps |
| T1225 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2445075499 |
|
|
Aug 06 07:55:05 PM PDT 24 |
Aug 06 07:55:19 PM PDT 24 |
31932600 ps |
| T1226 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2157378315 |
|
|
Aug 06 07:55:02 PM PDT 24 |
Aug 06 07:55:16 PM PDT 24 |
31138100 ps |
| T1227 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2302122126 |
|
|
Aug 06 07:54:50 PM PDT 24 |
Aug 06 07:55:03 PM PDT 24 |
48483300 ps |
| T1228 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1836348732 |
|
|
Aug 06 07:54:24 PM PDT 24 |
Aug 06 07:54:44 PM PDT 24 |
280942300 ps |
| T1229 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3728310029 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:04 PM PDT 24 |
28727700 ps |
| T1230 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.926342250 |
|
|
Aug 06 07:54:53 PM PDT 24 |
Aug 06 07:55:07 PM PDT 24 |
62651500 ps |
| T1231 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2527282958 |
|
|
Aug 06 07:54:23 PM PDT 24 |
Aug 06 07:54:37 PM PDT 24 |
78961200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3489668680 |
|
|
Aug 06 07:54:40 PM PDT 24 |
Aug 06 07:54:58 PM PDT 24 |
252134200 ps |
| T1233 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.820639164 |
|
|
Aug 06 07:54:52 PM PDT 24 |
Aug 06 07:55:10 PM PDT 24 |
93611300 ps |
| T1234 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1794853755 |
|
|
Aug 06 07:54:39 PM PDT 24 |
Aug 06 07:54:55 PM PDT 24 |
16641900 ps |
| T1235 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1005849666 |
|
|
Aug 06 07:54:54 PM PDT 24 |
Aug 06 07:55:11 PM PDT 24 |
37575000 ps |
| T1236 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2091366271 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:54:45 PM PDT 24 |
41300600 ps |
| T1237 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.475101638 |
|
|
Aug 06 07:54:27 PM PDT 24 |
Aug 06 07:55:03 PM PDT 24 |
751010100 ps |
| T1238 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2238217511 |
|
|
Aug 06 07:54:34 PM PDT 24 |
Aug 06 07:54:50 PM PDT 24 |
12520600 ps |
| T1239 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.104101928 |
|
|
Aug 06 07:54:58 PM PDT 24 |
Aug 06 07:55:11 PM PDT 24 |
25346300 ps |
| T1240 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1300757258 |
|
|
Aug 06 07:55:00 PM PDT 24 |
Aug 06 07:55:14 PM PDT 24 |
30612000 ps |
| T366 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3034829013 |
|
|
Aug 06 07:54:36 PM PDT 24 |
Aug 06 08:02:10 PM PDT 24 |
674040300 ps |
| T233 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2533144719 |
|
|
Aug 06 07:54:17 PM PDT 24 |
Aug 06 07:54:31 PM PDT 24 |
40052400 ps |
| T1241 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2294854779 |
|
|
Aug 06 07:54:50 PM PDT 24 |
Aug 06 07:55:04 PM PDT 24 |
15454800 ps |
| T294 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2341410754 |
|
|
Aug 06 07:54:37 PM PDT 24 |
Aug 06 07:54:56 PM PDT 24 |
230305000 ps |
| T1242 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.965235310 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:54:40 PM PDT 24 |
23302100 ps |
| T1243 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.295826700 |
|
|
Aug 06 07:54:52 PM PDT 24 |
Aug 06 07:55:07 PM PDT 24 |
58331600 ps |
| T1244 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2078120912 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:39 PM PDT 24 |
64074500 ps |
| T1245 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.31476304 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:54:39 PM PDT 24 |
22234600 ps |
| T1246 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.431387688 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:42 PM PDT 24 |
95417000 ps |
| T1247 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.839106244 |
|
|
Aug 06 07:54:17 PM PDT 24 |
Aug 06 07:55:18 PM PDT 24 |
2525653000 ps |
| T365 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.490684766 |
|
|
Aug 06 07:54:38 PM PDT 24 |
Aug 06 08:09:47 PM PDT 24 |
1607825100 ps |
| T1248 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2304113471 |
|
|
Aug 06 07:54:26 PM PDT 24 |
Aug 06 07:54:42 PM PDT 24 |
143527600 ps |
| T1249 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.700930579 |
|
|
Aug 06 07:54:40 PM PDT 24 |
Aug 06 07:54:55 PM PDT 24 |
48565900 ps |
| T1250 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.206379959 |
|
|
Aug 06 07:54:46 PM PDT 24 |
Aug 06 07:55:03 PM PDT 24 |
68408000 ps |
| T1251 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2556348606 |
|
|
Aug 06 07:54:25 PM PDT 24 |
Aug 06 07:54:45 PM PDT 24 |
246878700 ps |
| T1252 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.253956575 |
|
|
Aug 06 07:54:52 PM PDT 24 |
Aug 06 07:55:06 PM PDT 24 |
31472100 ps |
| T1253 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1236658868 |
|
|
Aug 06 07:55:02 PM PDT 24 |
Aug 06 07:55:16 PM PDT 24 |
44105700 ps |
| T1254 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1651555522 |
|
|
Aug 06 07:54:51 PM PDT 24 |
Aug 06 07:55:06 PM PDT 24 |
38463400 ps |