Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
382195 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
all_values[1] |
382195 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
all_values[2] |
382195 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
all_values[3] |
382195 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
all_values[4] |
382195 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
all_values[5] |
382195 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
770642 |
1 |
|
T1 |
6 |
|
T2 |
6 |
|
T3 |
12 |
auto[1] |
1522528 |
1 |
|
T7 |
11344 |
|
T25 |
14136 |
|
T36 |
28800 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1120063 |
1 |
|
T1 |
4 |
|
T2 |
4 |
|
T3 |
7 |
auto[1] |
1173107 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
5 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
24 |
4 |
20 |
83.33 |
4 |
Automatically Generated Cross Bins for intr_cg_cc
Element holes
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | NUMBER |
[all_values[0] , all_values[1]] |
* |
[auto[0]] |
-- |
-- |
4 |
Covered bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[1] |
382030 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
all_values[0] |
auto[1] |
auto[1] |
165 |
1 |
|
T258 |
2 |
|
T259 |
2 |
|
T309 |
1 |
all_values[1] |
auto[0] |
auto[1] |
382042 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
all_values[1] |
auto[1] |
auto[1] |
153 |
1 |
|
T258 |
1 |
|
T259 |
7 |
|
T309 |
3 |
all_values[2] |
auto[0] |
auto[0] |
1586 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
all_values[2] |
auto[0] |
auto[1] |
70 |
1 |
|
T258 |
1 |
|
T259 |
3 |
|
T309 |
4 |
all_values[2] |
auto[1] |
auto[0] |
380482 |
1 |
|
T7 |
2836 |
|
T25 |
3534 |
|
T36 |
7200 |
all_values[2] |
auto[1] |
auto[1] |
57 |
1 |
|
T259 |
2 |
|
T309 |
1 |
|
T310 |
1 |
all_values[3] |
auto[0] |
auto[0] |
1583 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
all_values[3] |
auto[0] |
auto[1] |
55 |
1 |
|
T258 |
1 |
|
T309 |
1 |
|
T310 |
3 |
all_values[3] |
auto[1] |
auto[0] |
82336 |
1 |
|
T25 |
1767 |
|
T36 |
1800 |
|
T33 |
551 |
all_values[3] |
auto[1] |
auto[1] |
298221 |
1 |
|
T7 |
2836 |
|
T25 |
1767 |
|
T36 |
5400 |
all_values[4] |
auto[0] |
auto[0] |
1123 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
all_values[4] |
auto[0] |
auto[1] |
511 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
3 |
all_values[4] |
auto[1] |
auto[0] |
270910 |
1 |
|
T7 |
1418 |
|
T25 |
1767 |
|
T36 |
5400 |
all_values[4] |
auto[1] |
auto[1] |
109651 |
1 |
|
T7 |
1418 |
|
T25 |
1767 |
|
T36 |
1800 |
all_values[5] |
auto[0] |
auto[0] |
1545 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
all_values[5] |
auto[0] |
auto[1] |
97 |
1 |
|
T37 |
1 |
|
T38 |
1 |
|
T39 |
1 |
all_values[5] |
auto[1] |
auto[0] |
380498 |
1 |
|
T7 |
2836 |
|
T25 |
3534 |
|
T36 |
7200 |
all_values[5] |
auto[1] |
auto[1] |
55 |
1 |
|
T309 |
2 |
|
T310 |
1 |
|
T312 |
2 |