Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	247276	1		T3	723		T4	35		T5	3
auto[FlashEraseBank]	271897	1		T3	675		T4	8		T5	5

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	261533	1		T4	43		T5	2		T7	1418
auto[FlashOpProgram]	237472	1		T3	1398		T5	4		T18	100
auto[FlashOpErase]	16168	1		T5	2		T18	100		T19	1
auto[FlashOpInvalid]	4000	1		T18	200		T139	200		T122	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	261533	1		T4	43		T5	2		T7	1418
op[FlashOpProgram]	237472	1		T3	1398		T5	4		T18	100
op[FlashOpErase]	16168	1		T5	2		T18	100		T19	1
read_erase_read	565	1		T5	1		T30	1		T31	2
read_prog_read	807	1		T22	1		T32	6		T46	10

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	376842	1		T3	1181		T4	43		T5	8
auto[FlashPartInfo]	138503	1		T3	207		T18	24		T30	154
auto[FlashPartInfo1]	846	1		T46	1		T64	2		T56	1
auto[FlashPartInfo2]	2982	1		T3	10		T44	2		T46	9

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	191264	1		T4	43		T5	2		T7	1418
auto[FlashPartData]	auto[FlashOpProgram]	178043	1		T3	1181		T5	4		T18	96
auto[FlashPartData]	auto[FlashOpErase]	3609	1		T5	2		T18	96		T19	1
auto[FlashPartData]	auto[FlashOpInvalid]	3926	1		T18	192		T139	198		T122	198
auto[FlashPartInfo]	auto[FlashOpRead]	67624	1		T18	8		T30	13		T22	3
auto[FlashPartInfo]	auto[FlashOpProgram]	58294	1		T3	207		T18	4		T30	128
auto[FlashPartInfo]	auto[FlashOpErase]	12523	1		T18	4		T30	13		T60	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	62	1		T18	8		T139	2		T122	2
auto[FlashPartInfo1]	auto[FlashOpRead]	670	1		T46	1		T64	2		T56	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T128	32		T129	32		T131	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T142	1		T131	1		T133	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T131	2		T133	2		T400	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1975	1		T46	7		T64	8		T56	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	970	1		T3	10		T46	2		T68	1
auto[FlashPartInfo2]	auto[FlashOpErase]	31	1		T44	2		T102	1		T138	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T401	2		T402	2		T403	2