Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32099	1		T5	3		T18	400		T19	4
auto[1]	74	1		T102	12		T333	1		T83	2
auto[2]	54	1		T23	1		T333	1		T217	4
auto[3]	215	1		T22	1		T24	15		T23	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8116	1		T5	1		T18	100		T19	1
evic_idx[1]	8113	1		T5	1		T18	100		T19	1
evic_idx[2]	8103	1		T5	1		T18	100		T19	1
evic_idx[3]	8110	1		T18	100		T19	1		T44	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31450	1		T18	400		T19	4		T45	1
evic_op[2]	274	1		T22	1		T31	4		T32	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7794	1		T18	100		T19	1		T45	1
evic_idx[0]	evic_op[1]	auto[1]	17	1		T102	5		T334	1		T215	3
evic_idx[0]	evic_op[1]	auto[2]	11	1		T217	1		T335	2		T334	3
evic_idx[0]	evic_op[1]	auto[3]	50	1		T24	4		T140	7		T336	1
evic_idx[0]	evic_op[2]	auto[0]	56	1		T31	1		T32	1		T279	7
evic_idx[0]	evic_op[2]	auto[1]	1	1		T337	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	1	1		T338	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	6	1		T339	1		T340	1		T341	1
evic_idx[1]	evic_op[1]	auto[0]	7793	1		T18	100		T19	1		T52	80
evic_idx[1]	evic_op[1]	auto[1]	16	1		T102	2		T334	2		T215	4
evic_idx[1]	evic_op[1]	auto[2]	10	1		T217	1		T335	1		T334	3
evic_idx[1]	evic_op[1]	auto[3]	47	1		T24	3		T140	9		T336	1
evic_idx[1]	evic_op[2]	auto[0]	54	1		T31	1		T32	1		T279	7
evic_idx[1]	evic_op[2]	auto[1]	5	1		T83	1		T342	1		T343	1
evic_idx[1]	evic_op[2]	auto[3]	8	1		T281	1		T344	1		T345	1
evic_idx[2]	evic_op[1]	auto[0]	7792	1		T18	100		T19	1		T52	80
evic_idx[2]	evic_op[1]	auto[1]	15	1		T102	3		T334	2		T215	2
evic_idx[2]	evic_op[1]	auto[2]	8	1		T217	1		T335	1		T334	3
evic_idx[2]	evic_op[1]	auto[3]	39	1		T24	4		T140	8		T217	5
evic_idx[2]	evic_op[2]	auto[0]	57	1		T31	1		T32	1		T279	7
evic_idx[2]	evic_op[2]	auto[1]	2	1		T83	1		T346	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	3	1		T23	1		T347	1		T348	1
evic_idx[2]	evic_op[2]	auto[3]	7	1		T23	1		T282	1		T349	1
evic_idx[3]	evic_op[1]	auto[0]	7791	1		T18	100		T19	1		T52	80
evic_idx[3]	evic_op[1]	auto[1]	16	1		T102	2		T334	2		T215	3
evic_idx[3]	evic_op[1]	auto[2]	6	1		T217	1		T334	2		T350	2
evic_idx[3]	evic_op[1]	auto[3]	45	1		T24	4		T140	9		T217	4
evic_idx[3]	evic_op[2]	auto[0]	56	1		T31	1		T32	1		T279	7
evic_idx[3]	evic_op[2]	auto[1]	2	1		T333	1		T351	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	3	1		T333	1		T344	1		T343	1
evic_idx[3]	evic_op[2]	auto[3]	13	1		T22	1		T26	1		T352	1