Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	38146	1		T316	14361		T317	2871		T318	16058
rd_lvl[2]	56942	1		T210	2031		T316	10247		T319	12696
rd_lvl[3]	16530	1		T210	1974		T319	400		T320	2104
rd_lvl[4]	35481	1		T210	733		T321	5503		T205	794
rd_lvl[5]	24482	1		T36	2443		T210	1635		T304	2392
rd_lvl[6]	20026	1		T36	1385		T210	2070		T304	1393
rd_lvl[7]	12318	1		T210	254		T322	105		T205	77
rd_lvl[8]	14361	1		T7	2836		T210	254		T323	132
rd_lvl[9]	7695	1		T210	254		T323	16		T320	1401
rd_lvl[10]	5229	1		T317	866		T324	1		T325	288
rd_lvl[11]	4042	1		T33	143		T326	517		T327	111
rd_lvl[12]	13586	1		T25	1345		T33	342		T326	1112
rd_lvl[13]	2851	1		T25	422		T88	402		T328	78
rd_lvl[14]	1623	1		T33	66		T34	597		T329	235
rd_lvl[15]	4911	1		T34	1131		T35	643		T329	214