Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	382195	1		T1	1		T2	1		T3	2
all_pins[1]	382195	1		T1	1		T2	1		T3	2
all_pins[2]	382195	1		T1	1		T2	1		T3	2
all_pins[3]	382195	1		T1	1		T2	1		T3	2
all_pins[4]	382195	1		T1	1		T2	1		T3	2
all_pins[5]	382195	1		T1	1		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1910638	1		T1	6		T2	6		T3	12
values[0x1]	382532	1		T7	4254		T25	3534		T36	5713
transitions[0x0=>0x1]	343594	1		T7	2836		T25	3534		T36	5628
transitions[0x1=>0x0]	343579	1		T7	2836		T25	3534		T36	5628

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	382030	1		T1	1		T2	1		T3	2
all_pins[0]	values[0x1]	165	1		T258	2		T259	2		T309	1
all_pins[0]	transitions[0x0=>0x1]	100	1		T258	1		T259	1		T309	1
all_pins[0]	transitions[0x1=>0x0]	88	1		T259	6		T309	3		T312	3
all_pins[1]	values[0x0]	382042	1		T1	1		T2	1		T3	2
all_pins[1]	values[0x1]	153	1		T258	1		T259	7		T309	3
all_pins[1]	transitions[0x0=>0x1]	126	1		T258	1		T259	6		T309	2
all_pins[1]	transitions[0x1=>0x0]	2593	1		T35	1076		T329	125		T353	1046
all_pins[2]	values[0x0]	379575	1		T1	1		T2	1		T3	2
all_pins[2]	values[0x1]	2620	1		T35	1076		T329	125		T353	1046
all_pins[2]	transitions[0x0=>0x1]	41	1		T259	2		T310	1		T312	1
all_pins[2]	transitions[0x1=>0x0]	258275	1		T7	2836		T25	1767		T36	3828
all_pins[3]	values[0x0]	121341	1		T1	1		T2	1		T3	2
all_pins[3]	values[0x1]	260854	1		T7	2836		T25	1767		T36	3828
all_pins[3]	transitions[0x0=>0x1]	224635	1		T7	1418		T25	1767		T36	3743
all_pins[3]	transitions[0x1=>0x0]	82466	1		T25	1767		T36	1800		T33	551
all_pins[4]	values[0x0]	263510	1		T1	1		T2	1		T3	2
all_pins[4]	values[0x1]	118685	1		T7	1418		T25	1767		T36	1885
all_pins[4]	transitions[0x0=>0x1]	118672	1		T7	1418		T25	1767		T36	1885
all_pins[4]	transitions[0x1=>0x0]	42	1		T309	1		T310	1		T312	2
all_pins[5]	values[0x0]	382140	1		T1	1		T2	1		T3	2
all_pins[5]	values[0x1]	55	1		T309	2		T310	1		T312	2
all_pins[5]	transitions[0x0=>0x1]	20	1		T309	2		T312	1		T314	1
all_pins[5]	transitions[0x1=>0x0]	115	1		T258	2		T259	2		T309	1