Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	296	1		T258	4		T259	7		T309	7
all_values[1]	296	1		T258	4		T259	7		T309	7
all_values[2]	296	1		T258	4		T259	7		T309	7
all_values[3]	296	1		T258	4		T259	7		T309	7
all_values[4]	296	1		T258	4		T259	7		T309	7
all_values[5]	296	1		T258	4		T259	7		T309	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	941	1		T258	13		T259	22		T309	28
auto[1]	835	1		T258	11		T259	20		T309	14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	605	1		T258	12		T259	7		T309	9
auto[1]	1171	1		T258	12		T259	35		T309	33

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1072	1		T258	19		T259	23		T309	19
auto[1]	704	1		T258	5		T259	19		T309	23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	101	1		T258	1		T259	3		T309	2
all_values[0]	auto[0]	auto[1]	auto[1]	80	1		T258	2		T259	3		T309	2
all_values[0]	auto[1]	auto[0]	auto[1]	54	1		T259	1		T309	3		T310	3
all_values[0]	auto[1]	auto[1]	auto[1]	61	1		T258	1		T310	1		T311	3
all_values[1]	auto[0]	auto[0]	auto[1]	103	1		T258	2		T259	1		T309	3
all_values[1]	auto[0]	auto[1]	auto[1]	77	1		T258	1		T259	3		T312	2
all_values[1]	auto[1]	auto[0]	auto[1]	65	1		T258	1		T259	1		T309	3
all_values[1]	auto[1]	auto[1]	auto[1]	51	1		T259	2		T309	1		T310	1
all_values[2]	auto[0]	auto[0]	auto[0]	94	1		T258	2		T259	2		T309	2
all_values[2]	auto[0]	auto[1]	auto[0]	75	1		T258	1		T310	3		T312	2
all_values[2]	auto[1]	auto[0]	auto[1]	73	1		T258	1		T259	2		T309	5
all_values[2]	auto[1]	auto[1]	auto[1]	54	1		T259	3		T310	1		T312	1
all_values[3]	auto[0]	auto[0]	auto[0]	85	1		T258	3		T259	2		T309	2
all_values[3]	auto[0]	auto[1]	auto[0]	88	1		T259	2		T309	2		T310	1
all_values[3]	auto[1]	auto[0]	auto[1]	58	1		T258	1		T309	1		T310	1
all_values[3]	auto[1]	auto[1]	auto[1]	65	1		T259	3		T309	2		T310	2
all_values[4]	auto[0]	auto[0]	auto[0]	66	1		T310	2		T312	2		T311	3
all_values[4]	auto[0]	auto[0]	auto[1]	21	1		T259	1		T310	1		T313	3
all_values[4]	auto[0]	auto[1]	auto[0]	54	1		T258	2		T310	2		T312	2
all_values[4]	auto[0]	auto[1]	auto[1]	36	1		T258	1		T259	2		T309	3
all_values[4]	auto[1]	auto[0]	auto[1]	62	1		T259	3		T309	1		T310	1
all_values[4]	auto[1]	auto[1]	auto[1]	57	1		T258	1		T259	1		T309	3
all_values[5]	auto[0]	auto[0]	auto[0]	70	1		T258	2		T309	3		T310	1
all_values[5]	auto[0]	auto[0]	auto[1]	27	1		T259	3		T311	1		T314	1
all_values[5]	auto[0]	auto[1]	auto[0]	73	1		T258	2		T259	1		T310	3
all_values[5]	auto[0]	auto[1]	auto[1]	22	1		T312	2		T311	1		T315	2
all_values[5]	auto[1]	auto[0]	auto[1]	62	1		T259	3		T309	3		T312	2
all_values[5]	auto[1]	auto[1]	auto[1]	42	1		T309	1		T310	3		T312	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal