Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	351243	1		T1	1		T2	1		T3	1
all_values[1]	351243	1		T1	1		T2	1		T3	1
all_values[2]	351243	1		T1	1		T2	1		T3	1
all_values[3]	351243	1		T1	1		T2	1		T3	1
all_values[4]	351243	1		T1	1		T2	1		T3	1
all_values[5]	351243	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	708861	1		T1	6		T2	6		T3	6
auto[1]	1398597	1		T6	6640		T40	3128		T41	13688

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1035815	1		T1	4		T2	4		T3	4
auto[1]	1071643	1		T1	2		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	351094	1		T1	1		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	149	1		T263	1		T264	4		T313	4
all_values[1]	auto[0]	auto[1]	351096	1		T1	1		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	147	1		T262	1		T263	5		T264	3
all_values[2]	auto[0]	auto[0]	1606	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	41	1		T262	2		T263	1		T264	1
all_values[2]	auto[1]	auto[0]	349541	1		T6	1660		T40	782		T41	3422
all_values[2]	auto[1]	auto[1]	55	1		T262	1		T264	2		T317	1
all_values[3]	auto[0]	auto[0]	1619	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	40	1		T262	1		T263	1		T264	2
all_values[3]	auto[1]	auto[0]	74314	1		T6	1660		T40	218		T41	1711
all_values[3]	auto[1]	auto[1]	275270	1		T40	564		T41	1711		T42	6068
all_values[4]	auto[0]	auto[0]	1126	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	551	1		T7	1		T22	1		T10	1
all_values[4]	auto[1]	auto[0]	256510	1		T6	1		T40	500		T41	1711
all_values[4]	auto[1]	auto[1]	93056	1		T6	1659		T40	282		T41	1711
all_values[5]	auto[0]	auto[0]	1596	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	92	1		T46	1		T103	1		T104	1
all_values[5]	auto[1]	auto[0]	349503	1		T6	1660		T40	782		T41	3422
all_values[5]	auto[1]	auto[1]	52	1		T314	1		T315	3		T320	2