Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	234152	1		T4	33		T6	1202		T7	1480
auto[FlashEraseBank]	261194	1		T4	12		T6	457		T7	1593

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	242141	1		T4	30		T7	1246		T22	8
auto[FlashOpProgram]	233929	1		T6	1659		T7	1827		T22	4
auto[FlashOpErase]	15276	1		T4	15		T22	4		T28	16
auto[FlashOpInvalid]	4000	1		T56	200		T93	200		T146	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	242141	1		T4	30		T7	1246		T22	8
op[FlashOpProgram]	233929	1		T6	1659		T7	1827		T22	4
op[FlashOpErase]	15276	1		T4	15		T22	4		T28	16
read_erase_read	555	1		T4	15		T22	2		T28	12
read_prog_read	741	1		T7	5		T22	1		T10	9

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	354432	1		T4	12		T6	1444		T7	2531
auto[FlashPartInfo]	137082	1		T4	33		T6	208		T7	523
auto[FlashPartInfo1]	804	1		T7	2		T10	1		T51	1
auto[FlashPartInfo2]	3028	1		T6	7		T7	17		T10	9

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	170798	1		T4	5		T7	947		T22	8
auto[FlashPartData]	auto[FlashOpProgram]	176131	1		T6	1444		T7	1584		T22	4
auto[FlashPartData]	auto[FlashOpErase]	3581	1		T4	7		T22	4		T28	10
auto[FlashPartData]	auto[FlashOpInvalid]	3922	1		T56	190		T93	194		T146	192
auto[FlashPartInfo]	auto[FlashOpRead]	68715	1		T4	25		T7	291		T10	358
auto[FlashPartInfo]	auto[FlashOpProgram]	56645	1		T6	208		T7	232		T10	239
auto[FlashPartInfo]	auto[FlashOpErase]	11660	1		T4	8		T28	3		T34	9
auto[FlashPartInfo]	auto[FlashOpInvalid]	62	1		T56	8		T93	4		T146	6
auto[FlashPartInfo1]	auto[FlashOpRead]	633	1		T7	2		T10	1		T51	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T56	1		T70	32		T72	32
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T56	1		T130	1		T414	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T56	2		T130	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1995	1		T7	6		T10	2		T28	5
auto[FlashPartInfo2]	auto[FlashOpProgram]	990	1		T6	7		T7	11		T10	7
auto[FlashPartInfo2]	auto[FlashOpErase]	31	1		T28	3		T93	1		T146	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T93	2		T146	2		T130	2