Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	2	30	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	2	30	93.75	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30151	1		T22	32		T50	4		T56	400
auto[1]	35	1		T332	4		T333	1		T334	1
auto[2]	58	1		T4	1		T28	2		T165	8
auto[3]	239	1		T4	5		T28	1		T27	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7610	1		T4	1		T22	8		T50	1
evic_idx[1]	7628	1		T4	2		T22	8		T50	1
evic_idx[2]	7631	1		T4	1		T22	8		T28	2
evic_idx[3]	7614	1		T4	2		T22	8		T28	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29617	1		T4	6		T22	12		T28	3
evic_op[2]	290	1		T22	16		T27	1		T30	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	2	30	93.75	2

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0] , evic_idx[1]]	[evic_op[2]]	[auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7339	1		T22	3		T50	1		T56	100
evic_idx[0]	evic_op[1]	auto[1]	6	1		T332	1		T335	2		T336	3
evic_idx[0]	evic_op[1]	auto[2]	4	1		T332	1		T337	1		T335	1
evic_idx[0]	evic_op[1]	auto[3]	50	1		T4	1		T217	3		T148	4
evic_idx[0]	evic_op[2]	auto[0]	61	1		T22	4		T25	4		T131	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T338	1		T339	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	4	1		T229	1		T48	1		T340	1
evic_idx[1]	evic_op[1]	auto[0]	7340	1		T22	3		T50	1		T56	100
evic_idx[1]	evic_op[1]	auto[1]	7	1		T332	1		T341	1		T335	2
evic_idx[1]	evic_op[1]	auto[2]	8	1		T4	1		T332	3		T337	1
evic_idx[1]	evic_op[1]	auto[3]	54	1		T4	1		T217	3		T148	7
evic_idx[1]	evic_op[2]	auto[0]	62	1		T22	4		T25	4		T226	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T342	1		T339	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	11	1		T343	1		T344	1		T345	1
evic_idx[2]	evic_op[1]	auto[0]	7340	1		T22	3		T50	1		T56	100
evic_idx[2]	evic_op[1]	auto[1]	6	1		T332	1		T335	3		T336	2
evic_idx[2]	evic_op[1]	auto[2]	7	1		T28	1		T332	3		T337	1
evic_idx[2]	evic_op[1]	auto[3]	62	1		T4	1		T28	1		T217	3
evic_idx[2]	evic_op[2]	auto[0]	60	1		T22	4		T25	4		T226	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T333	1		T334	1		T346	1
evic_idx[2]	evic_op[2]	auto[2]	1	1		T347	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	7	1		T47	1		T278	1		T348	1
evic_idx[3]	evic_op[1]	auto[0]	7339	1		T22	3		T50	1		T56	100
evic_idx[3]	evic_op[1]	auto[1]	5	1		T332	1		T335	2		T336	2
evic_idx[3]	evic_op[1]	auto[2]	7	1		T28	1		T332	3		T337	1
evic_idx[3]	evic_op[1]	auto[3]	43	1		T4	2		T217	2		T148	3
evic_idx[3]	evic_op[2]	auto[0]	62	1		T22	4		T25	4		T129	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T349	1		T350	1		T351	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T352	1		T347	2		-	-
evic_idx[3]	evic_op[2]	auto[3]	8	1		T27	1		T30	1		T31	1