Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	54108	1		T322	2666		T323	1641		T324	2746
rd_lvl[2]	43623	1		T322	2597		T323	2200		T325	603
rd_lvl[3]	15100	1		T322	1464		T323	833		T325	49
rd_lvl[4]	25714	1		T42	6009		T322	1504		T323	1536
rd_lvl[5]	14377	1		T42	15		T322	1415		T323	693
rd_lvl[6]	11198	1		T322	26		T323	814		T326	2582
rd_lvl[7]	9504	1		T40	350		T322	1376		T323	633
rd_lvl[8]	11792	1		T40	77		T322	1369		T323	1042
rd_lvl[9]	8230	1		T40	73		T327	286		T322	1662
rd_lvl[10]	7107	1		T40	64		T328	1331		T327	95
rd_lvl[11]	3362	1		T328	313		T327	1		T329	13
rd_lvl[12]	5124	1		T41	1436		T37	708		T38	338
rd_lvl[13]	3217	1		T41	275		T37	245		T38	125
rd_lvl[14]	6897	1		T38	1		T39	687		T277	311
rd_lvl[15]	2734	1		T37	14		T38	79		T330	536