Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	351243	1		T1	1		T2	1		T3	1
all_pins[1]	351243	1		T1	1		T2	1		T3	1
all_pins[2]	351243	1		T1	1		T2	1		T3	1
all_pins[3]	351243	1		T1	1		T2	1		T3	1
all_pins[4]	351243	1		T1	1		T2	1		T3	1
all_pins[5]	351243	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1773726	1		T1	6		T2	6		T3	6
values[0x1]	333732	1		T6	1659		T40	847		T41	3422
transitions[0x0=>0x1]	300407	1		T6	1659		T40	782		T41	3422
transitions[0x1=>0x0]	300392	1		T6	1659		T40	782		T41	3422

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	351094	1		T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	149	1		T263	1		T264	4		T313	4
all_pins[0]	transitions[0x0=>0x1]	69	1		T264	3		T313	3		T319	1
all_pins[0]	transitions[0x1=>0x0]	67	1		T262	1		T263	4		T264	2
all_pins[1]	values[0x0]	351096	1		T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	147	1		T262	1		T263	5		T264	3
all_pins[1]	transitions[0x0=>0x1]	118	1		T263	5		T264	2		T313	2
all_pins[1]	transitions[0x1=>0x0]	3515	1		T330	1141		T277	214		T353	212
all_pins[2]	values[0x0]	347699	1		T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	3544	1		T330	1141		T277	214		T353	212
all_pins[2]	transitions[0x0=>0x1]	40	1		T264	2		T316	2		T319	1
all_pins[2]	transitions[0x1=>0x0]	222329	1		T40	564		T41	1711		T42	6024
all_pins[3]	values[0x0]	125410	1		T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	225833	1		T40	564		T41	1711		T42	6024
all_pins[3]	transitions[0x0=>0x1]	196165	1		T40	499		T41	1711		T42	4537
all_pins[3]	transitions[0x1=>0x0]	74339	1		T6	1659		T40	218		T41	1711
all_pins[4]	values[0x0]	247236	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	104007	1		T6	1659		T40	283		T41	1711
all_pins[4]	transitions[0x0=>0x1]	103993	1		T6	1659		T40	283		T41	1711
all_pins[4]	transitions[0x1=>0x0]	38	1		T314	1		T315	2		T320	2
all_pins[5]	values[0x0]	351191	1		T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	52	1		T314	1		T315	3		T320	2
all_pins[5]	transitions[0x0=>0x1]	22	1		T315	2		T320	1		T321	1
all_pins[5]	transitions[0x1=>0x0]	104	1		T263	1		T264	4		T313	3