| T1073 |
/workspace/coverage/default/31.flash_ctrl_alert_test.3644051717 |
|
|
Aug 08 07:35:18 PM PDT 24 |
Aug 08 07:35:31 PM PDT 24 |
69898900 ps |
| T1074 |
/workspace/coverage/default/1.flash_ctrl_rw_evict.1645301226 |
|
|
Aug 08 07:23:45 PM PDT 24 |
Aug 08 07:24:14 PM PDT 24 |
28199800 ps |
| T1075 |
/workspace/coverage/default/4.flash_ctrl_rw.1925173180 |
|
|
Aug 08 07:26:15 PM PDT 24 |
Aug 08 07:33:42 PM PDT 24 |
2839411400 ps |
| T1076 |
/workspace/coverage/default/20.flash_ctrl_otp_reset.1706741302 |
|
|
Aug 08 07:33:32 PM PDT 24 |
Aug 08 07:35:45 PM PDT 24 |
54689200 ps |
| T1077 |
/workspace/coverage/default/9.flash_ctrl_intr_wr.2441346952 |
|
|
Aug 08 07:29:27 PM PDT 24 |
Aug 08 07:30:45 PM PDT 24 |
4607109100 ps |
| T1078 |
/workspace/coverage/default/6.flash_ctrl_rw.2051862992 |
|
|
Aug 08 07:27:35 PM PDT 24 |
Aug 08 07:37:40 PM PDT 24 |
18312576100 ps |
| T1079 |
/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.593089659 |
|
|
Aug 08 07:29:56 PM PDT 24 |
Aug 08 07:30:10 PM PDT 24 |
15210200 ps |
| T1080 |
/workspace/coverage/default/9.flash_ctrl_ro.2579726970 |
|
|
Aug 08 07:29:26 PM PDT 24 |
Aug 08 07:31:09 PM PDT 24 |
937857200 ps |
| T1081 |
/workspace/coverage/default/16.flash_ctrl_rw.1766849517 |
|
|
Aug 08 07:32:11 PM PDT 24 |
Aug 08 07:42:37 PM PDT 24 |
59260998200 ps |
| T209 |
/workspace/coverage/default/6.flash_ctrl_rw_derr.2327127438 |
|
|
Aug 08 07:27:34 PM PDT 24 |
Aug 08 07:31:13 PM PDT 24 |
5011747800 ps |
| T224 |
/workspace/coverage/default/2.flash_ctrl_wr_intg.778214826 |
|
|
Aug 08 07:24:37 PM PDT 24 |
Aug 08 07:24:52 PM PDT 24 |
84288900 ps |
| T1082 |
/workspace/coverage/default/11.flash_ctrl_smoke.2637324332 |
|
|
Aug 08 07:30:04 PM PDT 24 |
Aug 08 07:32:10 PM PDT 24 |
39951900 ps |
| T1083 |
/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2559299660 |
|
|
Aug 08 07:31:49 PM PDT 24 |
Aug 08 07:33:09 PM PDT 24 |
10019380800 ps |
| T1084 |
/workspace/coverage/default/16.flash_ctrl_otp_reset.505189261 |
|
|
Aug 08 07:32:01 PM PDT 24 |
Aug 08 07:34:13 PM PDT 24 |
167329900 ps |
| T1085 |
/workspace/coverage/default/2.flash_ctrl_phy_arb.2723613477 |
|
|
Aug 08 07:24:03 PM PDT 24 |
Aug 08 07:29:29 PM PDT 24 |
280425900 ps |
| T1086 |
/workspace/coverage/default/46.flash_ctrl_otp_reset.473000952 |
|
|
Aug 08 07:36:50 PM PDT 24 |
Aug 08 07:39:03 PM PDT 24 |
115856100 ps |
| T1087 |
/workspace/coverage/default/3.flash_ctrl_phy_arb.1741652760 |
|
|
Aug 08 07:24:52 PM PDT 24 |
Aug 08 07:28:08 PM PDT 24 |
47044500 ps |
| T1088 |
/workspace/coverage/default/12.flash_ctrl_disable.523819409 |
|
|
Aug 08 07:30:50 PM PDT 24 |
Aug 08 07:31:12 PM PDT 24 |
16938600 ps |
| T1089 |
/workspace/coverage/default/32.flash_ctrl_alert_test.1379714775 |
|
|
Aug 08 07:35:22 PM PDT 24 |
Aug 08 07:35:35 PM PDT 24 |
177264800 ps |
| T1090 |
/workspace/coverage/default/2.flash_ctrl_integrity.3204399495 |
|
|
Aug 08 07:24:20 PM PDT 24 |
Aug 08 07:37:09 PM PDT 24 |
22152139800 ps |
| T174 |
/workspace/coverage/default/3.flash_ctrl_mid_op_rst.3263773092 |
|
|
Aug 08 07:25:07 PM PDT 24 |
Aug 08 07:26:18 PM PDT 24 |
1940425300 ps |
| T1091 |
/workspace/coverage/default/16.flash_ctrl_ro.4016706178 |
|
|
Aug 08 07:32:10 PM PDT 24 |
Aug 08 07:34:00 PM PDT 24 |
751299900 ps |
| T1092 |
/workspace/coverage/default/45.flash_ctrl_smoke.2594499271 |
|
|
Aug 08 07:36:37 PM PDT 24 |
Aug 08 07:39:53 PM PDT 24 |
77791200 ps |
| T1093 |
/workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.876247179 |
|
|
Aug 08 07:27:15 PM PDT 24 |
Aug 08 07:27:29 PM PDT 24 |
72176300 ps |
| T1094 |
/workspace/coverage/default/9.flash_ctrl_sec_info_access.2156124107 |
|
|
Aug 08 07:29:54 PM PDT 24 |
Aug 08 07:31:09 PM PDT 24 |
1951506300 ps |
| T1095 |
/workspace/coverage/default/18.flash_ctrl_rand_ops.3899555968 |
|
|
Aug 08 07:32:41 PM PDT 24 |
Aug 08 07:36:28 PM PDT 24 |
168609800 ps |
| T1096 |
/workspace/coverage/default/31.flash_ctrl_connect.4164003890 |
|
|
Aug 08 07:35:12 PM PDT 24 |
Aug 08 07:35:25 PM PDT 24 |
23745300 ps |
| T1097 |
/workspace/coverage/default/4.flash_ctrl_re_evict.3512301809 |
|
|
Aug 08 07:26:30 PM PDT 24 |
Aug 08 07:27:06 PM PDT 24 |
83674400 ps |
| T1098 |
/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.1305256792 |
|
|
Aug 08 07:26:59 PM PDT 24 |
Aug 08 07:27:30 PM PDT 24 |
39984400 ps |
| T1099 |
/workspace/coverage/default/46.flash_ctrl_disable.2717538405 |
|
|
Aug 08 07:36:49 PM PDT 24 |
Aug 08 07:37:11 PM PDT 24 |
53184100 ps |
| T1100 |
/workspace/coverage/default/13.flash_ctrl_prog_reset.1945266567 |
|
|
Aug 08 07:31:11 PM PDT 24 |
Aug 08 07:31:25 PM PDT 24 |
22304500 ps |
| T1101 |
/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.773685849 |
|
|
Aug 08 07:33:25 PM PDT 24 |
Aug 08 07:35:53 PM PDT 24 |
4648221000 ps |
| T1102 |
/workspace/coverage/default/33.flash_ctrl_disable.1449545369 |
|
|
Aug 08 07:35:40 PM PDT 24 |
Aug 08 07:36:03 PM PDT 24 |
40453900 ps |
| T1103 |
/workspace/coverage/default/9.flash_ctrl_hw_rma_reset.3403063657 |
|
|
Aug 08 07:29:25 PM PDT 24 |
Aug 08 07:45:05 PM PDT 24 |
80150170000 ps |
| T1104 |
/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.4112920724 |
|
|
Aug 08 07:36:11 PM PDT 24 |
Aug 08 07:38:20 PM PDT 24 |
23467118500 ps |
| T1105 |
/workspace/coverage/default/3.flash_ctrl_rw_derr.3796577429 |
|
|
Aug 08 07:25:19 PM PDT 24 |
Aug 08 07:29:31 PM PDT 24 |
1712480900 ps |
| T1106 |
/workspace/coverage/default/3.flash_ctrl_smoke.3613370268 |
|
|
Aug 08 07:24:54 PM PDT 24 |
Aug 08 07:27:23 PM PDT 24 |
117769900 ps |
| T1107 |
/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3997226170 |
|
|
Aug 08 07:29:56 PM PDT 24 |
Aug 08 07:30:27 PM PDT 24 |
42252700 ps |
| T1108 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2674754682 |
|
|
Aug 08 07:06:18 PM PDT 24 |
Aug 08 07:06:34 PM PDT 24 |
75198100 ps |
| T262 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2293132751 |
|
|
Aug 08 07:09:43 PM PDT 24 |
Aug 08 07:09:57 PM PDT 24 |
39810000 ps |
| T75 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.581936250 |
|
|
Aug 08 07:09:01 PM PDT 24 |
Aug 08 07:21:52 PM PDT 24 |
1803151000 ps |
| T1109 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.4198913664 |
|
|
Aug 08 07:09:38 PM PDT 24 |
Aug 08 07:09:52 PM PDT 24 |
37435900 ps |
| T76 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1122111382 |
|
|
Aug 08 07:09:01 PM PDT 24 |
Aug 08 07:09:16 PM PDT 24 |
199572100 ps |
| T263 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.301449176 |
|
|
Aug 08 07:09:42 PM PDT 24 |
Aug 08 07:09:56 PM PDT 24 |
35706000 ps |
| T264 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3586968065 |
|
|
Aug 08 07:09:32 PM PDT 24 |
Aug 08 07:09:46 PM PDT 24 |
36651200 ps |
| T1110 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1009517053 |
|
|
Aug 08 07:09:26 PM PDT 24 |
Aug 08 07:09:41 PM PDT 24 |
151524900 ps |
| T313 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2148760445 |
|
|
Aug 08 07:09:01 PM PDT 24 |
Aug 08 07:09:15 PM PDT 24 |
15600600 ps |
| T317 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1166267741 |
|
|
Aug 08 07:06:50 PM PDT 24 |
Aug 08 07:07:04 PM PDT 24 |
50446600 ps |
| T237 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3263497791 |
|
|
Aug 08 07:07:32 PM PDT 24 |
Aug 08 07:07:46 PM PDT 24 |
59419000 ps |
| T77 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.354337246 |
|
|
Aug 08 07:07:02 PM PDT 24 |
Aug 08 07:22:20 PM PDT 24 |
2279972800 ps |
| T113 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1330604661 |
|
|
Aug 08 07:09:25 PM PDT 24 |
Aug 08 07:09:46 PM PDT 24 |
66738700 ps |
| T316 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1048738638 |
|
|
Aug 08 07:09:55 PM PDT 24 |
Aug 08 07:10:08 PM PDT 24 |
15331600 ps |
| T319 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3607848390 |
|
|
Aug 08 07:10:01 PM PDT 24 |
Aug 08 07:10:14 PM PDT 24 |
14477300 ps |
| T241 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.338017680 |
|
|
Aug 08 07:08:52 PM PDT 24 |
Aug 08 07:09:09 PM PDT 24 |
124340200 ps |
| T1111 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3970022545 |
|
|
Aug 08 07:09:09 PM PDT 24 |
Aug 08 07:09:23 PM PDT 24 |
70490900 ps |
| T257 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2770716541 |
|
|
Aug 08 07:06:36 PM PDT 24 |
Aug 08 07:07:14 PM PDT 24 |
1332640900 ps |
| T314 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2801075614 |
|
|
Aug 08 07:10:10 PM PDT 24 |
Aug 08 07:10:24 PM PDT 24 |
43805900 ps |
| T256 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1447062507 |
|
|
Aug 08 07:07:48 PM PDT 24 |
Aug 08 07:08:35 PM PDT 24 |
4370061500 ps |
| T242 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3336365936 |
|
|
Aug 08 07:08:45 PM PDT 24 |
Aug 08 07:09:05 PM PDT 24 |
124910600 ps |
| T1112 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1442344844 |
|
|
Aug 08 07:08:39 PM PDT 24 |
Aug 08 07:08:55 PM PDT 24 |
26905900 ps |
| T243 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2248717472 |
|
|
Aug 08 07:07:47 PM PDT 24 |
Aug 08 07:08:00 PM PDT 24 |
21464700 ps |
| T1113 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1543061473 |
|
|
Aug 08 07:07:02 PM PDT 24 |
Aug 08 07:07:17 PM PDT 24 |
50495200 ps |
| T1114 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.942481519 |
|
|
Aug 08 07:06:29 PM PDT 24 |
Aug 08 07:06:43 PM PDT 24 |
53953500 ps |
| T112 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.15324784 |
|
|
Aug 08 07:08:18 PM PDT 24 |
Aug 08 07:20:53 PM PDT 24 |
666122900 ps |
| T206 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.4164175931 |
|
|
Aug 08 07:08:37 PM PDT 24 |
Aug 08 07:08:52 PM PDT 24 |
79417500 ps |
| T315 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2994363792 |
|
|
Aug 08 07:09:44 PM PDT 24 |
Aug 08 07:09:57 PM PDT 24 |
50436900 ps |
| T318 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3866135930 |
|
|
Aug 08 07:10:01 PM PDT 24 |
Aug 08 07:10:14 PM PDT 24 |
16756700 ps |
| T244 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1545071078 |
|
|
Aug 08 07:07:10 PM PDT 24 |
Aug 08 07:07:24 PM PDT 24 |
34414900 ps |
| T289 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3013985283 |
|
|
Aug 08 07:07:20 PM PDT 24 |
Aug 08 07:08:12 PM PDT 24 |
4100453600 ps |
| T207 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2980848681 |
|
|
Aug 08 07:09:17 PM PDT 24 |
Aug 08 07:09:34 PM PDT 24 |
32647700 ps |
| T1115 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3850980674 |
|
|
Aug 08 07:09:53 PM PDT 24 |
Aug 08 07:10:06 PM PDT 24 |
14852000 ps |
| T320 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2224390044 |
|
|
Aug 08 07:09:28 PM PDT 24 |
Aug 08 07:09:42 PM PDT 24 |
50313300 ps |
| T1116 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1005445051 |
|
|
Aug 08 07:10:01 PM PDT 24 |
Aug 08 07:10:14 PM PDT 24 |
59134400 ps |
| T1117 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1578515198 |
|
|
Aug 08 07:08:27 PM PDT 24 |
Aug 08 07:08:41 PM PDT 24 |
55459500 ps |
| T321 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3607087983 |
|
|
Aug 08 07:10:11 PM PDT 24 |
Aug 08 07:10:25 PM PDT 24 |
15295300 ps |
| T245 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.615850410 |
|
|
Aug 08 07:08:19 PM PDT 24 |
Aug 08 07:08:49 PM PDT 24 |
164125000 ps |
| T246 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1924567652 |
|
|
Aug 08 07:08:20 PM PDT 24 |
Aug 08 07:08:42 PM PDT 24 |
846028100 ps |
| T230 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1110526128 |
|
|
Aug 08 07:08:37 PM PDT 24 |
Aug 08 07:08:53 PM PDT 24 |
35567300 ps |
| T236 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2005509542 |
|
|
Aug 08 07:06:50 PM PDT 24 |
Aug 08 07:13:16 PM PDT 24 |
174558500 ps |
| T231 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3120008215 |
|
|
Aug 08 07:07:20 PM PDT 24 |
Aug 08 07:07:39 PM PDT 24 |
658649800 ps |
| T1118 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2361306857 |
|
|
Aug 08 07:06:53 PM PDT 24 |
Aug 08 07:07:26 PM PDT 24 |
414685300 ps |
| T232 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2949122743 |
|
|
Aug 08 07:09:17 PM PDT 24 |
Aug 08 07:16:57 PM PDT 24 |
173661500 ps |
| T1119 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.254928377 |
|
|
Aug 08 07:08:45 PM PDT 24 |
Aug 08 07:09:01 PM PDT 24 |
54351200 ps |
| T247 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1550871748 |
|
|
Aug 08 07:09:36 PM PDT 24 |
Aug 08 07:09:51 PM PDT 24 |
273313400 ps |
| T233 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3299965768 |
|
|
Aug 08 07:08:03 PM PDT 24 |
Aug 08 07:23:00 PM PDT 24 |
12237774900 ps |
| T248 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4229219874 |
|
|
Aug 08 07:08:53 PM PDT 24 |
Aug 08 07:09:12 PM PDT 24 |
116313500 ps |
| T1120 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1349456670 |
|
|
Aug 08 07:08:03 PM PDT 24 |
Aug 08 07:08:16 PM PDT 24 |
22437600 ps |
| T1121 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.189892674 |
|
|
Aug 08 07:09:01 PM PDT 24 |
Aug 08 07:09:14 PM PDT 24 |
13847400 ps |
| T1122 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2796424995 |
|
|
Aug 08 07:07:21 PM PDT 24 |
Aug 08 07:07:37 PM PDT 24 |
23229800 ps |
| T1123 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.237885181 |
|
|
Aug 08 07:06:45 PM PDT 24 |
Aug 08 07:07:01 PM PDT 24 |
110130500 ps |
| T234 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3395703745 |
|
|
Aug 08 07:08:02 PM PDT 24 |
Aug 08 07:08:19 PM PDT 24 |
39855200 ps |
| T235 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1579137748 |
|
|
Aug 08 07:09:38 PM PDT 24 |
Aug 08 07:09:54 PM PDT 24 |
108266500 ps |
| T258 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1906129251 |
|
|
Aug 08 07:07:54 PM PDT 24 |
Aug 08 07:08:12 PM PDT 24 |
85048500 ps |
| T268 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.605135661 |
|
|
Aug 08 07:08:37 PM PDT 24 |
Aug 08 07:23:32 PM PDT 24 |
846812800 ps |
| T290 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4194114465 |
|
|
Aug 08 07:09:42 PM PDT 24 |
Aug 08 07:10:00 PM PDT 24 |
411120400 ps |
| T267 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2527897615 |
|
|
Aug 08 07:07:29 PM PDT 24 |
Aug 08 07:07:59 PM PDT 24 |
62211300 ps |
| T260 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2863497283 |
|
|
Aug 08 07:09:38 PM PDT 24 |
Aug 08 07:09:54 PM PDT 24 |
40321700 ps |
| T1124 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.4263873171 |
|
|
Aug 08 07:09:42 PM PDT 24 |
Aug 08 07:09:55 PM PDT 24 |
30399100 ps |
| T1125 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2066932694 |
|
|
Aug 08 07:09:34 PM PDT 24 |
Aug 08 07:09:55 PM PDT 24 |
721709500 ps |
| T1126 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.87552220 |
|
|
Aug 08 07:09:34 PM PDT 24 |
Aug 08 07:09:53 PM PDT 24 |
81672100 ps |
| T1127 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2024685333 |
|
|
Aug 08 07:09:25 PM PDT 24 |
Aug 08 07:09:41 PM PDT 24 |
69957800 ps |
| T1128 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.713721337 |
|
|
Aug 08 07:08:05 PM PDT 24 |
Aug 08 07:08:24 PM PDT 24 |
132878800 ps |
| T1129 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2813754139 |
|
|
Aug 08 07:09:54 PM PDT 24 |
Aug 08 07:10:07 PM PDT 24 |
21524200 ps |
| T1130 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3075349795 |
|
|
Aug 08 07:07:09 PM PDT 24 |
Aug 08 07:07:22 PM PDT 24 |
27009500 ps |
| T291 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3758932041 |
|
|
Aug 08 07:08:04 PM PDT 24 |
Aug 08 07:08:40 PM PDT 24 |
391700400 ps |
| T1131 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3162448121 |
|
|
Aug 08 07:09:00 PM PDT 24 |
Aug 08 07:09:13 PM PDT 24 |
28730500 ps |
| T1132 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.643258055 |
|
|
Aug 08 07:09:26 PM PDT 24 |
Aug 08 07:09:43 PM PDT 24 |
33149500 ps |
| T265 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2648456200 |
|
|
Aug 08 07:07:41 PM PDT 24 |
Aug 08 07:07:58 PM PDT 24 |
38625000 ps |
| T1133 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2767630668 |
|
|
Aug 08 07:07:12 PM PDT 24 |
Aug 08 07:07:25 PM PDT 24 |
17289800 ps |
| T292 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2004366793 |
|
|
Aug 08 07:06:54 PM PDT 24 |
Aug 08 07:07:33 PM PDT 24 |
99768900 ps |
| T293 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1756954913 |
|
|
Aug 08 07:09:17 PM PDT 24 |
Aug 08 07:09:34 PM PDT 24 |
60963200 ps |
| T1134 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3931978062 |
|
|
Aug 08 07:08:18 PM PDT 24 |
Aug 08 07:08:34 PM PDT 24 |
43750400 ps |
| T1135 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.535426998 |
|
|
Aug 08 07:07:49 PM PDT 24 |
Aug 08 07:08:04 PM PDT 24 |
214296300 ps |
| T1136 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1679796164 |
|
|
Aug 08 07:09:34 PM PDT 24 |
Aug 08 07:09:48 PM PDT 24 |
14652800 ps |
| T1137 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2252716081 |
|
|
Aug 08 07:09:43 PM PDT 24 |
Aug 08 07:09:57 PM PDT 24 |
47484000 ps |
| T1138 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3001884221 |
|
|
Aug 08 07:09:33 PM PDT 24 |
Aug 08 07:09:49 PM PDT 24 |
131282200 ps |
| T1139 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3434774619 |
|
|
Aug 08 07:09:44 PM PDT 24 |
Aug 08 07:09:57 PM PDT 24 |
50813500 ps |
| T271 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2649008893 |
|
|
Aug 08 07:09:09 PM PDT 24 |
Aug 08 07:09:28 PM PDT 24 |
41890200 ps |
| T1140 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2152271237 |
|
|
Aug 08 07:09:52 PM PDT 24 |
Aug 08 07:10:06 PM PDT 24 |
24708600 ps |
| T1141 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3889493267 |
|
|
Aug 08 07:08:20 PM PDT 24 |
Aug 08 07:08:33 PM PDT 24 |
25116700 ps |
| T1142 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.776673362 |
|
|
Aug 08 07:08:19 PM PDT 24 |
Aug 08 07:08:38 PM PDT 24 |
442159500 ps |
| T1143 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2053039895 |
|
|
Aug 08 07:09:52 PM PDT 24 |
Aug 08 07:10:06 PM PDT 24 |
17516700 ps |
| T1144 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3550012041 |
|
|
Aug 08 07:06:35 PM PDT 24 |
Aug 08 07:07:25 PM PDT 24 |
1671990300 ps |
| T1145 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1452692987 |
|
|
Aug 08 07:08:02 PM PDT 24 |
Aug 08 07:08:16 PM PDT 24 |
29379600 ps |
| T273 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1267365555 |
|
|
Aug 08 07:09:33 PM PDT 24 |
Aug 08 07:24:31 PM PDT 24 |
662275100 ps |
| T1146 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1954977340 |
|
|
Aug 08 07:10:00 PM PDT 24 |
Aug 08 07:10:13 PM PDT 24 |
28029000 ps |
| T1147 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1823755031 |
|
|
Aug 08 07:08:08 PM PDT 24 |
Aug 08 07:08:21 PM PDT 24 |
16256400 ps |
| T1148 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3928073234 |
|
|
Aug 08 07:06:36 PM PDT 24 |
Aug 08 07:06:50 PM PDT 24 |
83475600 ps |
| T1149 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1624923090 |
|
|
Aug 08 07:09:02 PM PDT 24 |
Aug 08 07:09:20 PM PDT 24 |
364951100 ps |
| T1150 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3179888259 |
|
|
Aug 08 07:09:02 PM PDT 24 |
Aug 08 07:09:15 PM PDT 24 |
30637000 ps |
| T1151 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2749966357 |
|
|
Aug 08 07:07:55 PM PDT 24 |
Aug 08 07:08:11 PM PDT 24 |
37589600 ps |
| T269 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1923308318 |
|
|
Aug 08 07:09:10 PM PDT 24 |
Aug 08 07:16:53 PM PDT 24 |
689260000 ps |
| T1152 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3415483940 |
|
|
Aug 08 07:10:00 PM PDT 24 |
Aug 08 07:10:14 PM PDT 24 |
26633500 ps |
| T294 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2417579436 |
|
|
Aug 08 07:08:52 PM PDT 24 |
Aug 08 07:09:09 PM PDT 24 |
409138300 ps |
| T1153 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3366617802 |
|
|
Aug 08 07:08:36 PM PDT 24 |
Aug 08 07:08:53 PM PDT 24 |
100086100 ps |
| T1154 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3277194579 |
|
|
Aug 08 07:09:28 PM PDT 24 |
Aug 08 07:09:46 PM PDT 24 |
35449000 ps |
| T1155 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3223476350 |
|
|
Aug 08 07:07:42 PM PDT 24 |
Aug 08 07:07:58 PM PDT 24 |
25486600 ps |
| T1156 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.766586641 |
|
|
Aug 08 07:08:12 PM PDT 24 |
Aug 08 07:08:26 PM PDT 24 |
48003800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1515176671 |
|
|
Aug 08 07:08:04 PM PDT 24 |
Aug 08 07:08:19 PM PDT 24 |
15884100 ps |
| T1158 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3669620940 |
|
|
Aug 08 07:07:03 PM PDT 24 |
Aug 08 07:07:24 PM PDT 24 |
157198300 ps |
| T1159 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2635181566 |
|
|
Aug 08 07:09:18 PM PDT 24 |
Aug 08 07:09:35 PM PDT 24 |
40656700 ps |
| T1160 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1534412044 |
|
|
Aug 08 07:07:46 PM PDT 24 |
Aug 08 07:08:48 PM PDT 24 |
4634838400 ps |
| T1161 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1065733846 |
|
|
Aug 08 07:08:26 PM PDT 24 |
Aug 08 07:08:42 PM PDT 24 |
87434600 ps |
| T1162 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3098490783 |
|
|
Aug 08 07:07:43 PM PDT 24 |
Aug 08 07:08:17 PM PDT 24 |
230031800 ps |
| T1163 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3298686245 |
|
|
Aug 08 07:07:39 PM PDT 24 |
Aug 08 07:07:57 PM PDT 24 |
27884100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3582253391 |
|
|
Aug 08 07:09:51 PM PDT 24 |
Aug 08 07:10:05 PM PDT 24 |
17728600 ps |
| T1165 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2089300373 |
|
|
Aug 08 07:09:25 PM PDT 24 |
Aug 08 07:09:43 PM PDT 24 |
25750100 ps |
| T1166 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3368167743 |
|
|
Aug 08 07:09:42 PM PDT 24 |
Aug 08 07:09:59 PM PDT 24 |
48787300 ps |
| T1167 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.4231940793 |
|
|
Aug 08 07:08:36 PM PDT 24 |
Aug 08 07:08:49 PM PDT 24 |
15916300 ps |
| T1168 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.901529027 |
|
|
Aug 08 07:07:40 PM PDT 24 |
Aug 08 07:08:53 PM PDT 24 |
5698853600 ps |
| T1169 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1788024401 |
|
|
Aug 08 07:09:39 PM PDT 24 |
Aug 08 07:09:55 PM PDT 24 |
12469300 ps |
| T356 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3239045962 |
|
|
Aug 08 07:08:27 PM PDT 24 |
Aug 08 07:16:08 PM PDT 24 |
682101900 ps |
| T1170 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1113338086 |
|
|
Aug 08 07:07:46 PM PDT 24 |
Aug 08 07:07:59 PM PDT 24 |
16592700 ps |
| T1171 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2516806507 |
|
|
Aug 08 07:10:01 PM PDT 24 |
Aug 08 07:10:15 PM PDT 24 |
167332700 ps |
| T1172 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3360039684 |
|
|
Aug 08 07:08:06 PM PDT 24 |
Aug 08 07:08:21 PM PDT 24 |
225359000 ps |
| T355 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2647750222 |
|
|
Aug 08 07:09:26 PM PDT 24 |
Aug 08 07:22:03 PM PDT 24 |
764218500 ps |
| T1173 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4291932720 |
|
|
Aug 08 07:08:12 PM PDT 24 |
Aug 08 07:08:30 PM PDT 24 |
361607700 ps |
| T1174 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3377294814 |
|
|
Aug 08 07:09:35 PM PDT 24 |
Aug 08 07:09:51 PM PDT 24 |
144062200 ps |
| T1175 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1794169571 |
|
|
Aug 08 07:08:52 PM PDT 24 |
Aug 08 07:09:08 PM PDT 24 |
14698600 ps |
| T266 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.480789827 |
|
|
Aug 08 07:07:21 PM PDT 24 |
Aug 08 07:07:43 PM PDT 24 |
139166400 ps |
| T1176 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1052795544 |
|
|
Aug 08 07:06:28 PM PDT 24 |
Aug 08 07:07:13 PM PDT 24 |
25494900 ps |
| T272 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2852948740 |
|
|
Aug 08 07:09:02 PM PDT 24 |
Aug 08 07:09:21 PM PDT 24 |
129511400 ps |
| T354 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3025550923 |
|
|
Aug 08 07:08:39 PM PDT 24 |
Aug 08 07:23:38 PM PDT 24 |
922652200 ps |
| T270 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1200694961 |
|
|
Aug 08 07:09:10 PM PDT 24 |
Aug 08 07:09:29 PM PDT 24 |
106293100 ps |
| T1177 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3779861820 |
|
|
Aug 08 07:07:21 PM PDT 24 |
Aug 08 07:07:50 PM PDT 24 |
453357800 ps |
| T1178 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.179969337 |
|
|
Aug 08 07:07:22 PM PDT 24 |
Aug 08 07:07:38 PM PDT 24 |
17062500 ps |
| T1179 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3687503399 |
|
|
Aug 08 07:09:17 PM PDT 24 |
Aug 08 07:09:31 PM PDT 24 |
28885000 ps |
| T1180 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.201310287 |
|
|
Aug 08 07:09:01 PM PDT 24 |
Aug 08 07:09:14 PM PDT 24 |
49413600 ps |
| T1181 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.81560153 |
|
|
Aug 08 07:08:45 PM PDT 24 |
Aug 08 07:09:01 PM PDT 24 |
231315200 ps |
| T1182 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4110764914 |
|
|
Aug 08 07:07:38 PM PDT 24 |
Aug 08 07:07:57 PM PDT 24 |
139777700 ps |
| T1183 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1480565318 |
|
|
Aug 08 07:08:37 PM PDT 24 |
Aug 08 07:08:55 PM PDT 24 |
162836100 ps |
| T1184 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.574242727 |
|
|
Aug 08 07:06:20 PM PDT 24 |
Aug 08 07:06:36 PM PDT 24 |
57681900 ps |
| T1185 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2168771508 |
|
|
Aug 08 07:09:17 PM PDT 24 |
Aug 08 07:09:33 PM PDT 24 |
11392300 ps |
| T1186 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1472664013 |
|
|
Aug 08 07:08:03 PM PDT 24 |
Aug 08 07:08:20 PM PDT 24 |
62719300 ps |
| T1187 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1851255826 |
|
|
Aug 08 07:07:21 PM PDT 24 |
Aug 08 07:07:34 PM PDT 24 |
16779000 ps |
| T1188 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3484038627 |
|
|
Aug 08 07:09:53 PM PDT 24 |
Aug 08 07:10:07 PM PDT 24 |
41556400 ps |
| T1189 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3146081849 |
|
|
Aug 08 07:08:54 PM PDT 24 |
Aug 08 07:09:08 PM PDT 24 |
17762300 ps |
| T1190 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.912403971 |
|
|
Aug 08 07:09:52 PM PDT 24 |
Aug 08 07:10:05 PM PDT 24 |
20292700 ps |
| T359 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.419316433 |
|
|
Aug 08 07:07:55 PM PDT 24 |
Aug 08 07:23:06 PM PDT 24 |
703288300 ps |
| T1191 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3379747610 |
|
|
Aug 08 07:08:03 PM PDT 24 |
Aug 08 07:08:20 PM PDT 24 |
134538200 ps |
| T295 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3506267559 |
|
|
Aug 08 07:09:09 PM PDT 24 |
Aug 08 07:09:27 PM PDT 24 |
219691600 ps |
| T261 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2648902932 |
|
|
Aug 08 07:06:20 PM PDT 24 |
Aug 08 07:06:41 PM PDT 24 |
61315700 ps |
| T1192 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.745697038 |
|
|
Aug 08 07:08:44 PM PDT 24 |
Aug 08 07:09:01 PM PDT 24 |
92654900 ps |
| T360 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3849591360 |
|
|
Aug 08 07:08:12 PM PDT 24 |
Aug 08 07:23:11 PM PDT 24 |
1286921400 ps |
| T1193 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2270678841 |
|
|
Aug 08 07:09:51 PM PDT 24 |
Aug 08 07:10:05 PM PDT 24 |
16462300 ps |
| T1194 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2569829242 |
|
|
Aug 08 07:08:26 PM PDT 24 |
Aug 08 07:08:42 PM PDT 24 |
21178900 ps |
| T1195 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3863558884 |
|
|
Aug 08 07:07:32 PM PDT 24 |
Aug 08 07:07:47 PM PDT 24 |
77596400 ps |
| T1196 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.347778520 |
|
|
Aug 08 07:08:28 PM PDT 24 |
Aug 08 07:08:45 PM PDT 24 |
197150000 ps |
| T259 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1892449451 |
|
|
Aug 08 07:08:28 PM PDT 24 |
Aug 08 07:08:48 PM PDT 24 |
212782800 ps |
| T357 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3038459056 |
|
|
Aug 08 07:08:47 PM PDT 24 |
Aug 08 07:23:42 PM PDT 24 |
8333297800 ps |
| T1197 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2764186725 |
|
|
Aug 08 07:09:02 PM PDT 24 |
Aug 08 07:09:20 PM PDT 24 |
252389900 ps |
| T1198 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.243442699 |
|
|
Aug 08 07:08:21 PM PDT 24 |
Aug 08 07:08:34 PM PDT 24 |
12274100 ps |
| T1199 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.506586546 |
|
|
Aug 08 07:09:26 PM PDT 24 |
Aug 08 07:09:42 PM PDT 24 |
12055700 ps |
| T1200 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.407051672 |
|
|
Aug 08 07:07:12 PM PDT 24 |
Aug 08 07:07:56 PM PDT 24 |
51527200 ps |
| T1201 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2793035254 |
|
|
Aug 08 07:07:21 PM PDT 24 |
Aug 08 07:08:03 PM PDT 24 |
1764379900 ps |
| T274 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2155149852 |
|
|
Aug 08 07:08:53 PM PDT 24 |
Aug 08 07:09:10 PM PDT 24 |
118556200 ps |
| T1202 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1840349508 |
|
|
Aug 08 07:07:42 PM PDT 24 |
Aug 08 07:22:57 PM PDT 24 |
1005533800 ps |
| T1203 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1918379658 |
|
|
Aug 08 07:08:47 PM PDT 24 |
Aug 08 07:09:01 PM PDT 24 |
133900700 ps |
| T1204 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.820267796 |
|
|
Aug 08 07:07:45 PM PDT 24 |
Aug 08 07:08:15 PM PDT 24 |
19983000 ps |
| T1205 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3889194900 |
|
|
Aug 08 07:09:10 PM PDT 24 |
Aug 08 07:09:26 PM PDT 24 |
14089300 ps |
| T361 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1638444099 |
|
|
Aug 08 07:07:20 PM PDT 24 |
Aug 08 07:13:46 PM PDT 24 |
729483100 ps |
| T1206 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.598070782 |
|
|
Aug 08 07:08:37 PM PDT 24 |
Aug 08 07:08:50 PM PDT 24 |
34941700 ps |
| T1207 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3101086433 |
|
|
Aug 08 07:08:52 PM PDT 24 |
Aug 08 07:09:07 PM PDT 24 |
14352900 ps |
| T1208 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1296112436 |
|
|
Aug 08 07:06:49 PM PDT 24 |
Aug 08 07:07:24 PM PDT 24 |
222756300 ps |
| T1209 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2409545654 |
|
|
Aug 08 07:06:45 PM PDT 24 |
Aug 08 07:06:59 PM PDT 24 |
37430900 ps |
| T1210 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2143132548 |
|
|
Aug 08 07:09:52 PM PDT 24 |
Aug 08 07:10:06 PM PDT 24 |
24062400 ps |
| T1211 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3052913486 |
|
|
Aug 08 07:07:46 PM PDT 24 |
Aug 08 07:07:59 PM PDT 24 |
16191600 ps |
| T1212 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3127594037 |
|
|
Aug 08 07:08:52 PM PDT 24 |
Aug 08 07:09:05 PM PDT 24 |
14154100 ps |
| T1213 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2414821397 |
|
|
Aug 08 07:08:05 PM PDT 24 |
Aug 08 07:08:24 PM PDT 24 |
138581900 ps |
| T1214 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.286958462 |
|
|
Aug 08 07:08:18 PM PDT 24 |
Aug 08 07:08:35 PM PDT 24 |
78411000 ps |
| T1215 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3828227253 |
|
|
Aug 08 07:06:53 PM PDT 24 |
Aug 08 07:07:32 PM PDT 24 |
658663800 ps |
| T1216 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3991732760 |
|
|
Aug 08 07:10:00 PM PDT 24 |
Aug 08 07:10:13 PM PDT 24 |
58705200 ps |
| T1217 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.787108681 |
|
|
Aug 08 07:07:01 PM PDT 24 |
Aug 08 07:07:21 PM PDT 24 |
62096000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.328669813 |
|
|
Aug 08 07:09:43 PM PDT 24 |
Aug 08 07:09:59 PM PDT 24 |
73235700 ps |
| T1219 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3111775589 |
|
|
Aug 08 07:06:28 PM PDT 24 |
Aug 08 07:06:42 PM PDT 24 |
28941900 ps |
| T1220 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.279047180 |
|
|
Aug 08 07:06:52 PM PDT 24 |
Aug 08 07:07:09 PM PDT 24 |
55810900 ps |
| T1221 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3141386829 |
|
|
Aug 08 07:07:38 PM PDT 24 |
Aug 08 07:07:51 PM PDT 24 |
45745900 ps |
| T1222 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1825954330 |
|
|
Aug 08 07:06:18 PM PDT 24 |
Aug 08 07:21:20 PM PDT 24 |
1696814500 ps |
| T238 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.617991368 |
|
|
Aug 08 07:06:28 PM PDT 24 |
Aug 08 07:06:42 PM PDT 24 |
16631100 ps |
| T1223 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1976476074 |
|
|
Aug 08 07:08:19 PM PDT 24 |
Aug 08 07:08:39 PM PDT 24 |
62185900 ps |
| T1224 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.147659952 |
|
|
Aug 08 07:08:37 PM PDT 24 |
Aug 08 07:08:56 PM PDT 24 |
251822100 ps |
| T1225 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.287197279 |
|
|
Aug 08 07:08:06 PM PDT 24 |
Aug 08 07:08:19 PM PDT 24 |
40335400 ps |
| T1226 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2081520001 |
|
|
Aug 08 07:08:45 PM PDT 24 |
Aug 08 07:08:59 PM PDT 24 |
50627700 ps |
| T1227 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1074687178 |
|
|
Aug 08 07:08:36 PM PDT 24 |
Aug 08 07:08:54 PM PDT 24 |
217618200 ps |
| T1228 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2231677566 |
|
|
Aug 08 07:08:03 PM PDT 24 |
Aug 08 07:08:20 PM PDT 24 |
132064700 ps |
| T1229 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3604552292 |
|
|
Aug 08 07:09:37 PM PDT 24 |
Aug 08 07:09:54 PM PDT 24 |
52690500 ps |
| T1230 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.461793138 |
|
|
Aug 08 07:07:29 PM PDT 24 |
Aug 08 07:07:42 PM PDT 24 |
26091900 ps |
| T358 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2168158601 |
|
|
Aug 08 07:09:34 PM PDT 24 |
Aug 08 07:22:10 PM PDT 24 |
856102800 ps |
| T239 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2436695549 |
|
|
Aug 08 07:06:52 PM PDT 24 |
Aug 08 07:07:06 PM PDT 24 |
16879900 ps |
| T1231 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2861861896 |
|
|
Aug 08 07:07:10 PM PDT 24 |
Aug 08 07:07:26 PM PDT 24 |
40289200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.4257934895 |
|
|
Aug 08 07:09:52 PM PDT 24 |
Aug 08 07:10:06 PM PDT 24 |
38186500 ps |
| T1233 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2758040353 |
|
|
Aug 08 07:09:51 PM PDT 24 |
Aug 08 07:10:04 PM PDT 24 |
15252900 ps |
| T1234 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3993488316 |
|
|
Aug 08 07:09:02 PM PDT 24 |
Aug 08 07:09:22 PM PDT 24 |
858373000 ps |
| T1235 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2303111755 |
|
|
Aug 08 07:07:54 PM PDT 24 |
Aug 08 07:08:29 PM PDT 24 |
131458100 ps |
| T1236 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1973002877 |
|
|
Aug 08 07:09:18 PM PDT 24 |
Aug 08 07:09:34 PM PDT 24 |
25246800 ps |
| T1237 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1958525710 |
|
|
Aug 08 07:09:52 PM PDT 24 |
Aug 08 07:10:06 PM PDT 24 |
22891300 ps |
| T240 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4152381592 |
|
|
Aug 08 07:07:09 PM PDT 24 |
Aug 08 07:07:23 PM PDT 24 |
58750600 ps |
| T1238 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1425531032 |
|
|
Aug 08 07:06:53 PM PDT 24 |
Aug 08 07:07:06 PM PDT 24 |
30898000 ps |
| T1239 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.4021861087 |
|
|
Aug 08 07:10:02 PM PDT 24 |
Aug 08 07:10:15 PM PDT 24 |
23643700 ps |
| T1240 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1766334724 |
|
|
Aug 08 07:06:45 PM PDT 24 |
Aug 08 07:07:04 PM PDT 24 |
93830000 ps |
| T1241 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2016074518 |
|
|
Aug 08 07:08:11 PM PDT 24 |
Aug 08 07:08:25 PM PDT 24 |
110502500 ps |
| T1242 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3163803820 |
|
|
Aug 08 07:09:16 PM PDT 24 |
Aug 08 07:09:30 PM PDT 24 |
38580500 ps |
| T1243 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3193857984 |
|
|
Aug 08 07:08:18 PM PDT 24 |
Aug 08 07:08:35 PM PDT 24 |
68712000 ps |
| T1244 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1822170641 |
|
|
Aug 08 07:09:17 PM PDT 24 |
Aug 08 07:09:33 PM PDT 24 |
215362700 ps |
| T1245 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3209845867 |
|
|
Aug 08 07:08:53 PM PDT 24 |
Aug 08 07:21:36 PM PDT 24 |
1156818100 ps |
| T1246 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3077281470 |
|
|
Aug 08 07:08:29 PM PDT 24 |
Aug 08 07:08:43 PM PDT 24 |
16636200 ps |
| T1247 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3016595799 |
|
|
Aug 08 07:09:52 PM PDT 24 |
Aug 08 07:10:05 PM PDT 24 |
14543100 ps |
| T1248 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1759489160 |
|
|
Aug 08 07:07:04 PM PDT 24 |
Aug 08 07:07:21 PM PDT 24 |
59953100 ps |
| T1249 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3773477038 |
|
|
Aug 08 07:07:54 PM PDT 24 |
Aug 08 07:08:13 PM PDT 24 |
145243400 ps |
| T1250 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.4175186474 |
|
|
Aug 08 07:08:12 PM PDT 24 |
Aug 08 07:08:28 PM PDT 24 |
46601500 ps |