Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	277487	1		T1	1		T2	1		T3	2
all_values[1]	277487	1		T1	1		T2	1		T3	2
all_values[2]	277487	1		T1	1		T2	1		T3	2
all_values[3]	277487	1		T1	1		T2	1		T3	2
all_values[4]	277487	1		T1	1		T2	1		T3	2
all_values[5]	277487	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	561420	1		T1	6		T2	6		T3	12
auto[1]	1103502	1		T7	13272		T35	13272		T26	6684

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	811015	1		T1	4		T2	4		T3	7
auto[1]	853907	1		T1	2		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	277340	1		T1	1		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	147	1		T282	5		T284	4		T342	4
all_values[1]	auto[0]	auto[1]	277350	1		T1	1		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	137	1		T282	1		T284	5		T342	3
all_values[2]	auto[0]	auto[0]	1612	1		T1	1		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	63	1		T342	2		T345	1		T343	1
all_values[2]	auto[1]	auto[0]	275770	1		T7	3318		T35	3318		T26	1671
all_values[2]	auto[1]	auto[1]	42	1		T282	1		T283	1		T284	1
all_values[3]	auto[0]	auto[0]	1641	1		T1	1		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	52	1		T283	1		T346	3		T348	1
all_values[3]	auto[1]	auto[0]	82612	1		T7	1659		T26	1671		T36	1579
all_values[3]	auto[1]	auto[1]	193182	1		T7	1659		T35	3318		T36	1579
all_values[4]	auto[0]	auto[0]	1151	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	534	1		T3	1		T4	1		T21	1
all_values[4]	auto[1]	auto[0]	170904	1		T7	1659		T35	1659		T26	1
all_values[4]	auto[1]	auto[1]	104898	1		T7	1659		T35	1659		T26	1670
all_values[5]	auto[0]	auto[0]	1582	1		T1	1		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	95	1		T38	1		T39	1		T40	1
all_values[5]	auto[1]	auto[0]	275743	1		T7	3318		T35	3318		T26	1671
all_values[5]	auto[1]	auto[1]	67	1		T283	1		T345	3		T344	2