Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	237746	1		T7	916		T19	32		T20	8
auto[FlashEraseBank]	266583	1		T7	743		T19	14		T20	8

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	255986	1		T7	1659		T19	28		T20	12
auto[FlashOpProgram]	228987	1		T20	4		T21	4		T64	180
auto[FlashOpErase]	15356	1		T19	18		T44	30		T64	180
auto[FlashOpInvalid]	4000	1		T97	200		T154	200		T317	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	255986	1		T7	1659		T19	28		T20	12
op[FlashOpProgram]	228987	1		T20	4		T21	4		T64	180
op[FlashOpErase]	15356	1		T19	18		T44	30		T64	180
read_erase_read	599	1		T19	15		T25	12		T29	2
read_prog_read	842	1		T20	2		T42	9		T23	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	366957	1		T7	1659		T19	17		T20	9
auto[FlashPartInfo]	133246	1		T19	29		T20	7		T64	713
auto[FlashPartInfo1]	921	1		T42	15		T84	1		T74	3
auto[FlashPartInfo2]	3205	1		T25	1		T42	5		T94	1

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	188015	1		T7	1659		T19	9		T20	6
auto[FlashPartData]	auto[FlashOpProgram]	171414	1		T20	3		T21	4		T41	1
auto[FlashPartData]	auto[FlashOpErase]	3586	1		T19	8		T44	30		T25	7
auto[FlashPartData]	auto[FlashOpInvalid]	3942	1		T97	194		T154	196		T317	198
auto[FlashPartInfo]	auto[FlashOpRead]	64994	1		T19	19		T20	6		T64	353
auto[FlashPartInfo]	auto[FlashOpProgram]	56469	1		T20	1		T64	180		T29	288
auto[FlashPartInfo]	auto[FlashOpErase]	11737	1		T19	10		T64	180		T25	9
auto[FlashPartInfo]	auto[FlashOpInvalid]	46	1		T97	6		T154	4		T317	2
auto[FlashPartInfo1]	auto[FlashOpRead]	750	1		T42	15		T74	3		T170	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T84	1		T73	32		T138	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T400	1		T214	1		T401	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T401	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	2227	1		T25	1		T42	3		T145	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	938	1		T42	2		T136	1		T249	6
auto[FlashPartInfo2]	auto[FlashOpErase]	30	1		T94	1		T153	1		T164	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T164	2		T402	2		T403	2