Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30188	1		T44	4		T64	372		T65	688
auto[1]	31	1		T25	5		T24	1		T145	4
auto[2]	45	1		T44	4		T25	2		T220	1
auto[3]	275	1		T19	16		T25	6		T23	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7634	1		T19	5		T44	2		T64	93
evic_idx[1]	7637	1		T19	4		T44	2		T64	93
evic_idx[2]	7642	1		T19	3		T44	2		T64	93
evic_idx[3]	7626	1		T19	4		T44	2		T64	93

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29640	1		T19	16		T64	372		T25	13
evic_op[2]	303	1		T23	1		T24	1		T70	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7346	1		T64	93		T65	172		T97	100
evic_idx[0]	evic_op[1]	auto[1]	3	1		T25	2		T404	1		-	-
evic_idx[0]	evic_op[1]	auto[2]	2	1		T239	2		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	59	1		T19	5		T25	1		T298	2
evic_idx[0]	evic_op[2]	auto[0]	58	1		T66	1		T379	1		T405	1
evic_idx[0]	evic_op[2]	auto[1]	3	1		T99	1		T406	1		T407	1
evic_idx[0]	evic_op[2]	auto[2]	3	1		T220	1		T408	1		T409	1
evic_idx[0]	evic_op[2]	auto[3]	10	1		T37	1		T307	1		T410	1
evic_idx[1]	evic_op[1]	auto[0]	7346	1		T64	93		T65	172		T97	100
evic_idx[1]	evic_op[1]	auto[1]	6	1		T25	1		T145	1		T404	4
evic_idx[1]	evic_op[1]	auto[2]	2	1		T411	2		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	57	1		T19	4		T25	1		T298	1
evic_idx[1]	evic_op[2]	auto[0]	58	1		T66	1		T379	1		T405	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T99	1		T406	1		T412	1
evic_idx[1]	evic_op[2]	auto[2]	4	1		T304	1		T407	1		T408	1
evic_idx[1]	evic_op[2]	auto[3]	12	1		T23	1		T136	1		T51	1
evic_idx[2]	evic_op[1]	auto[0]	7345	1		T64	93		T65	172		T97	100
evic_idx[2]	evic_op[1]	auto[1]	5	1		T25	1		T145	1		T404	3
evic_idx[2]	evic_op[1]	auto[2]	1	1		T25	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	62	1		T19	3		T25	2		T298	3
evic_idx[2]	evic_op[2]	auto[0]	61	1		T66	1		T379	1		T405	1
evic_idx[2]	evic_op[2]	auto[1]	5	1		T406	1		T413	1		T414	1
evic_idx[2]	evic_op[2]	auto[2]	5	1		T304	1		T415	1		T408	1
evic_idx[2]	evic_op[2]	auto[3]	9	1		T70	1		T219	1		T416	1
evic_idx[3]	evic_op[1]	auto[0]	7345	1		T64	93		T65	172		T97	100
evic_idx[3]	evic_op[1]	auto[1]	3	1		T25	1		T145	2		-	-
evic_idx[3]	evic_op[1]	auto[2]	1	1		T25	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	57	1		T19	4		T25	2		T298	3
evic_idx[3]	evic_op[2]	auto[0]	57	1		T66	1		T379	1		T405	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T24	1		T220	1		T406	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T304	1		T408	1		T409	1
evic_idx[3]	evic_op[2]	auto[3]	9	1		T417	1		T418	1		T419	1