Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
4744 | 
1 | 
 | 
T55 | 
205 | 
 | 
T56 | 
162 | 
 | 
T57 | 
67 | 
| instr_types[0] | 
5731 | 
1 | 
 | 
T55 | 
265 | 
 | 
T56 | 
195 | 
 | 
T57 | 
287 | 
| instr_types[1] | 
4158631 | 
1 | 
 | 
T1 | 
500 | 
 | 
T5 | 
33 | 
 | 
T7 | 
16923 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4167035 | 
1 | 
 | 
T1 | 
500 | 
 | 
T5 | 
33 | 
 | 
T7 | 
16923 | 
| auto[1] | 
2071 | 
1 | 
 | 
T55 | 
300 | 
 | 
T56 | 
127 | 
 | 
T57 | 
152 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
4271 | 
1 | 
 | 
T55 | 
107 | 
 | 
T56 | 
125 | 
 | 
T57 | 
57 | 
| auto[0] | 
instr_types[0] | 
4968 | 
1 | 
 | 
T55 | 
176 | 
 | 
T56 | 
167 | 
 | 
T57 | 
223 | 
| auto[0] | 
instr_types[1] | 
4157796 | 
1 | 
 | 
T1 | 
500 | 
 | 
T5 | 
33 | 
 | 
T7 | 
16923 | 
| auto[1] | 
others | 
473 | 
1 | 
 | 
T55 | 
98 | 
 | 
T56 | 
37 | 
 | 
T57 | 
10 | 
| auto[1] | 
instr_types[0] | 
763 | 
1 | 
 | 
T55 | 
89 | 
 | 
T56 | 
28 | 
 | 
T57 | 
64 | 
| auto[1] | 
instr_types[1] | 
835 | 
1 | 
 | 
T55 | 
113 | 
 | 
T56 | 
62 | 
 | 
T57 | 
78 |