Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	7586	1		T77	2681		T351	2550		T352	2355
rd_lvl[2]	31590	1		T77	2442		T353	12383		T351	2246
rd_lvl[3]	14659	1		T77	1435		T354	4386		T353	365
rd_lvl[4]	39107	1		T77	1431		T354	4039		T351	1406
rd_lvl[5]	9953	1		T77	1352		T351	1299		T355	126
rd_lvl[6]	5045	1		T77	13		T351	70		T355	7
rd_lvl[7]	10050	1		T77	1301		T351	1248		T355	1
rd_lvl[8]	19848	1		T35	2844		T77	1300		T351	1266
rd_lvl[9]	8594	1		T35	474		T77	1610		T33	160
rd_lvl[10]	9711	1		T7	1463		T77	990		T33	254
rd_lvl[11]	3591	1		T7	196		T356	61		T351	85
rd_lvl[12]	3753	1		T33	131		T357	1209		T358	147
rd_lvl[13]	2747	1		T36	471		T357	391		T355	7
rd_lvl[14]	8876	1		T36	1108		T32	675		T303	212
rd_lvl[15]	3856	1		T32	169		T34	477		T303	54