Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	277487	1		T1	1		T2	1		T3	2
all_pins[1]	277487	1		T1	1		T2	1		T3	2
all_pins[2]	277487	1		T1	1		T2	1		T3	2
all_pins[3]	277487	1		T1	1		T2	1		T3	2
all_pins[4]	277487	1		T1	1		T2	1		T3	2
all_pins[5]	277487	1		T1	1		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1357972	1		T1	6		T2	6		T3	12
values[0x1]	306950	1		T7	3318		T35	4977		T26	1670
transitions[0x0=>0x1]	269084	1		T7	3318		T35	3318		T26	1670
transitions[0x1=>0x0]	269074	1		T7	3318		T35	3318		T26	1670

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	277340	1		T1	1		T2	1		T3	2
all_pins[0]	values[0x1]	147	1		T282	5		T284	4		T342	4
all_pins[0]	transitions[0x0=>0x1]	75	1		T282	4		T342	1		T343	1
all_pins[0]	transitions[0x1=>0x0]	65	1		T284	1		T343	3		T344	3
all_pins[1]	values[0x0]	277350	1		T1	1		T2	1		T3	2
all_pins[1]	values[0x1]	137	1		T282	1		T284	5		T342	3
all_pins[1]	transitions[0x0=>0x1]	119	1		T282	1		T284	4		T342	3
all_pins[1]	transitions[0x1=>0x0]	6482	1		T32	21		T34	1274		T303	33
all_pins[2]	values[0x0]	270987	1		T1	1		T2	1		T3	2
all_pins[2]	values[0x1]	6500	1		T32	21		T34	1274		T303	33
all_pins[2]	transitions[0x0=>0x1]	28	1		T282	1		T283	1		T346	1
all_pins[2]	transitions[0x1=>0x0]	179638	1		T7	1659		T35	3318		T36	1579
all_pins[3]	values[0x0]	91377	1		T1	1		T2	1		T3	2
all_pins[3]	values[0x1]	186110	1		T7	1659		T35	3318		T36	1579
all_pins[3]	transitions[0x0=>0x1]	154863	1		T7	1659		T35	1659		T36	1579
all_pins[3]	transitions[0x1=>0x0]	82742	1		T7	1659		T26	1670		T36	1579
all_pins[4]	values[0x0]	163498	1		T1	1		T2	1		T3	2
all_pins[4]	values[0x1]	113989	1		T7	1659		T35	1659		T26	1670
all_pins[4]	transitions[0x0=>0x1]	113974	1		T7	1659		T35	1659		T26	1670
all_pins[4]	transitions[0x1=>0x0]	52	1		T345	3		T344	1		T347	3
all_pins[5]	values[0x0]	277420	1		T1	1		T2	1		T3	2
all_pins[5]	values[0x1]	67	1		T283	1		T345	3		T344	2
all_pins[5]	transitions[0x0=>0x1]	25	1		T283	1		T345	1		T344	1
all_pins[5]	transitions[0x1=>0x0]	95	1		T282	4		T284	3		T342	3