Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 36 8 28 77.78


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 6 0 6 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 36 8 28 77.78 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 260 1 T282 4 T283 4 T284 4
all_values[1] 260 1 T282 4 T283 4 T284 4
all_values[2] 260 1 T282 4 T283 4 T284 4
all_values[3] 260 1 T282 4 T283 4 T284 4
all_values[4] 260 1 T282 4 T283 4 T284 4
all_values[5] 260 1 T282 4 T283 4 T284 4



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 904 1 T282 9 T283 20 T284 6
auto[1] 656 1 T282 15 T283 4 T284 18



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 502 1 T282 12 T283 9 T284 10
auto[1] 1058 1 T282 12 T283 15 T284 14



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 924 1 T282 17 T283 17 T284 17
auto[1] 636 1 T282 7 T283 7 T284 7



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 36 8 28 77.78 8
Automatically Generated Cross Bins 36 8 28 77.78 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBER
[all_values[0] , all_values[1]] [auto[0]] * [auto[0]] -- -- 4
[all_values[2] , all_values[3]] [auto[0]] * [auto[1]] -- -- 4


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[1] 91 1 T283 4 T284 1 T342 1
all_values[0] auto[0] auto[1] auto[1] 71 1 T282 2 T284 2 T342 3
all_values[0] auto[1] auto[0] auto[1] 55 1 T282 1 T343 1 T344 1
all_values[0] auto[1] auto[1] auto[1] 43 1 T282 1 T284 1 T345 1
all_values[1] auto[0] auto[0] auto[1] 85 1 T282 1 T283 3 T342 1
all_values[1] auto[0] auto[1] auto[1] 63 1 T284 3 T342 2 T343 1
all_values[1] auto[1] auto[0] auto[1] 69 1 T282 1 T283 1 T342 1
all_values[1] auto[1] auto[1] auto[1] 43 1 T282 2 T284 1 T345 3
all_values[2] auto[0] auto[0] auto[0] 81 1 T283 2 T342 2 T343 3
all_values[2] auto[0] auto[1] auto[0] 74 1 T282 3 T283 1 T284 3
all_values[2] auto[1] auto[0] auto[1] 73 1 T282 1 T342 2 T345 2
all_values[2] auto[1] auto[1] auto[1] 32 1 T283 1 T284 1 T345 1
all_values[3] auto[0] auto[0] auto[0] 90 1 T282 1 T283 2 T342 3
all_values[3] auto[0] auto[1] auto[0] 64 1 T282 3 T284 2 T345 2
all_values[3] auto[1] auto[0] auto[1] 59 1 T346 4 T347 1 T348 1
all_values[3] auto[1] auto[1] auto[1] 47 1 T283 2 T284 2 T342 1
all_values[4] auto[0] auto[0] auto[0] 60 1 T282 1 T283 2 T345 1
all_values[4] auto[0] auto[0] auto[1] 29 1 T282 1 T283 1 T284 1
all_values[4] auto[0] auto[1] auto[0] 37 1 T284 1 T349 1 T350 1
all_values[4] auto[0] auto[1] auto[1] 32 1 T282 1 T342 2 T343 1
all_values[4] auto[1] auto[0] auto[1] 59 1 T283 1 T284 1 T342 2
all_values[4] auto[1] auto[1] auto[1] 43 1 T282 1 T284 1 T345 1
all_values[5] auto[0] auto[0] auto[0] 57 1 T282 2 T283 2 T284 3
all_values[5] auto[0] auto[0] auto[1] 25 1 T342 1 T343 1 T346 1
all_values[5] auto[0] auto[1] auto[0] 39 1 T282 2 T284 1 T342 1
all_values[5] auto[0] auto[1] auto[1] 26 1 T345 1 T344 1 T347 1
all_values[5] auto[1] auto[0] auto[1] 71 1 T283 2 T342 1 T343 2
all_values[5] auto[1] auto[1] auto[1] 42 1 T345 2 T344 1 T347 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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