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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.26 95.73 93.92 98.31 92.52 98.31 96.99 98.06


Total test records in report: 1264
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T1078 /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.876171097 Aug 09 06:30:24 PM PDT 24 Aug 09 06:32:44 PM PDT 24 5846868300 ps
T1079 /workspace/coverage/default/4.flash_ctrl_oversize_error.3682880389 Aug 09 06:24:15 PM PDT 24 Aug 09 06:28:00 PM PDT 24 11577889700 ps
T1080 /workspace/coverage/default/26.flash_ctrl_prog_reset.1353867381 Aug 09 06:32:23 PM PDT 24 Aug 09 06:32:37 PM PDT 24 20812800 ps
T1081 /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.1673150944 Aug 09 06:29:06 PM PDT 24 Aug 09 06:29:19 PM PDT 24 48157700 ps
T1082 /workspace/coverage/default/36.flash_ctrl_otp_reset.763207651 Aug 09 06:33:39 PM PDT 24 Aug 09 06:35:31 PM PDT 24 249114600 ps
T1083 /workspace/coverage/default/17.flash_ctrl_rand_ops.3629496200 Aug 09 06:30:16 PM PDT 24 Aug 09 06:47:01 PM PDT 24 1533380400 ps
T1084 /workspace/coverage/default/3.flash_ctrl_rw.2605053858 Aug 09 06:22:59 PM PDT 24 Aug 09 06:33:24 PM PDT 24 13308426500 ps
T1085 /workspace/coverage/default/4.flash_ctrl_rw.2448402514 Aug 09 06:24:01 PM PDT 24 Aug 09 06:33:43 PM PDT 24 14871774600 ps
T1086 /workspace/coverage/default/0.flash_ctrl_full_mem_access.1420965330 Aug 09 06:20:49 PM PDT 24 Aug 09 07:09:09 PM PDT 24 165489542600 ps
T1087 /workspace/coverage/default/46.flash_ctrl_connect.2545074794 Aug 09 06:34:35 PM PDT 24 Aug 09 06:34:50 PM PDT 24 41718900 ps
T1088 /workspace/coverage/default/13.flash_ctrl_rand_ops.425833929 Aug 09 06:28:49 PM PDT 24 Aug 09 06:36:18 PM PDT 24 104719400 ps
T1089 /workspace/coverage/default/1.flash_ctrl_alert_test.2602930480 Aug 09 06:21:42 PM PDT 24 Aug 09 06:21:55 PM PDT 24 24097400 ps
T1090 /workspace/coverage/default/0.flash_ctrl_write_word_sweep.1435290717 Aug 09 06:20:52 PM PDT 24 Aug 09 06:21:08 PM PDT 24 39357400 ps
T1091 /workspace/coverage/default/17.flash_ctrl_phy_arb.400842590 Aug 09 06:30:16 PM PDT 24 Aug 09 06:39:03 PM PDT 24 8085882700 ps
T1092 /workspace/coverage/default/34.flash_ctrl_intr_rd.2961619975 Aug 09 06:33:26 PM PDT 24 Aug 09 06:37:01 PM PDT 24 7097239000 ps
T1093 /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1697101036 Aug 09 06:32:24 PM PDT 24 Aug 09 06:35:02 PM PDT 24 11429098400 ps
T1094 /workspace/coverage/default/12.flash_ctrl_rw.3042730546 Aug 09 06:28:27 PM PDT 24 Aug 09 06:39:20 PM PDT 24 18126649200 ps
T1095 /workspace/coverage/default/52.flash_ctrl_otp_reset.1954782460 Aug 09 06:34:51 PM PDT 24 Aug 09 06:37:04 PM PDT 24 349927900 ps
T1096 /workspace/coverage/default/6.flash_ctrl_phy_arb.1189322719 Aug 09 06:25:17 PM PDT 24 Aug 09 06:29:18 PM PDT 24 231002300 ps
T1097 /workspace/coverage/default/2.flash_ctrl_phy_arb.396431222 Aug 09 06:21:46 PM PDT 24 Aug 09 06:22:55 PM PDT 24 26522900 ps
T1098 /workspace/coverage/default/27.flash_ctrl_rw_evict.2162890443 Aug 09 06:32:29 PM PDT 24 Aug 09 06:33:01 PM PDT 24 31282100 ps
T1099 /workspace/coverage/default/16.flash_ctrl_invalid_op.1158669567 Aug 09 06:29:57 PM PDT 24 Aug 09 06:31:05 PM PDT 24 3894702800 ps
T1100 /workspace/coverage/default/15.flash_ctrl_disable.293134687 Aug 09 06:29:44 PM PDT 24 Aug 09 06:30:05 PM PDT 24 24425000 ps
T1101 /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.2233468776 Aug 09 06:34:27 PM PDT 24 Aug 09 06:37:05 PM PDT 24 3837125100 ps
T1102 /workspace/coverage/default/39.flash_ctrl_disable.1348455692 Aug 09 06:34:04 PM PDT 24 Aug 09 06:34:26 PM PDT 24 15045200 ps
T1103 /workspace/coverage/default/49.flash_ctrl_connect.1050585846 Aug 09 06:34:53 PM PDT 24 Aug 09 06:35:09 PM PDT 24 85487200 ps
T1104 /workspace/coverage/default/0.flash_ctrl_otp_reset.3765556224 Aug 09 06:20:47 PM PDT 24 Aug 09 06:22:57 PM PDT 24 173882300 ps
T1105 /workspace/coverage/default/76.flash_ctrl_connect.2290007428 Aug 09 06:35:27 PM PDT 24 Aug 09 06:35:40 PM PDT 24 15525600 ps
T1106 /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.2681748404 Aug 09 06:30:31 PM PDT 24 Aug 09 06:31:18 PM PDT 24 10046036100 ps
T1107 /workspace/coverage/default/8.flash_ctrl_alert_test.3390325468 Aug 09 06:26:52 PM PDT 24 Aug 09 06:27:06 PM PDT 24 56555200 ps
T1108 /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3173780022 Aug 09 06:33:17 PM PDT 24 Aug 09 06:36:01 PM PDT 24 6009027700 ps
T1109 /workspace/coverage/default/35.flash_ctrl_alert_test.3049186481 Aug 09 06:33:31 PM PDT 24 Aug 09 06:33:44 PM PDT 24 20473700 ps
T1110 /workspace/coverage/default/12.flash_ctrl_smoke.4105182 Aug 09 06:28:22 PM PDT 24 Aug 09 06:31:16 PM PDT 24 109961300 ps
T1111 /workspace/coverage/default/2.flash_ctrl_derr_detect.3608416156 Aug 09 06:22:07 PM PDT 24 Aug 09 06:25:18 PM PDT 24 1344993500 ps
T1112 /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3454162142 Aug 09 06:24:20 PM PDT 24 Aug 09 06:27:11 PM PDT 24 19634048700 ps
T1113 /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.3789828848 Aug 09 06:24:15 PM PDT 24 Aug 09 06:24:38 PM PDT 24 32569200 ps
T1114 /workspace/coverage/default/26.flash_ctrl_intr_rd.1757377362 Aug 09 06:32:23 PM PDT 24 Aug 09 06:35:16 PM PDT 24 1823310400 ps
T1115 /workspace/coverage/default/22.flash_ctrl_smoke.701179553 Aug 09 06:31:37 PM PDT 24 Aug 09 06:34:02 PM PDT 24 29235000 ps
T1116 /workspace/coverage/default/60.flash_ctrl_otp_reset.927851061 Aug 09 06:35:09 PM PDT 24 Aug 09 06:37:23 PM PDT 24 72868200 ps
T1117 /workspace/coverage/default/28.flash_ctrl_alert_test.4242948521 Aug 09 06:32:39 PM PDT 24 Aug 09 06:32:52 PM PDT 24 114620800 ps
T1118 /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1495048551 Aug 09 06:32:46 PM PDT 24 Aug 09 06:34:59 PM PDT 24 5891833800 ps
T1119 /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.607255110 Aug 09 06:26:47 PM PDT 24 Aug 09 06:27:00 PM PDT 24 92308900 ps
T1120 /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.1342570527 Aug 09 06:29:01 PM PDT 24 Aug 09 06:29:33 PM PDT 24 27626200 ps
T1121 /workspace/coverage/default/68.flash_ctrl_otp_reset.2417506960 Aug 09 06:35:21 PM PDT 24 Aug 09 06:37:37 PM PDT 24 75212900 ps
T352 /workspace/coverage/default/5.flash_ctrl_intr_rd.3843359515 Aug 09 06:24:57 PM PDT 24 Aug 09 06:27:37 PM PDT 24 1013239000 ps
T1122 /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.1758704407 Aug 09 06:32:46 PM PDT 24 Aug 09 06:33:18 PM PDT 24 29387300 ps
T1123 /workspace/coverage/default/1.flash_ctrl_fs_sup.2066981519 Aug 09 06:21:15 PM PDT 24 Aug 09 06:21:55 PM PDT 24 5401663300 ps
T1124 /workspace/coverage/default/32.flash_ctrl_rw_evict.1823208626 Aug 09 06:33:19 PM PDT 24 Aug 09 06:33:50 PM PDT 24 27968300 ps
T1125 /workspace/coverage/default/77.flash_ctrl_otp_reset.3828363181 Aug 09 06:35:26 PM PDT 24 Aug 09 06:37:38 PM PDT 24 143445100 ps
T282 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3432733047 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:48 PM PDT 24 130999900 ps
T78 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3617805099 Aug 09 07:53:35 PM PDT 24 Aug 09 07:53:52 PM PDT 24 66185300 ps
T283 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2384266681 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:48 PM PDT 24 15149700 ps
T79 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.280059930 Aug 09 07:53:29 PM PDT 24 Aug 09 07:59:55 PM PDT 24 1946041600 ps
T80 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.833205422 Aug 09 07:52:53 PM PDT 24 Aug 09 08:00:32 PM PDT 24 738857400 ps
T1126 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4207728585 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:48 PM PDT 24 13665400 ps
T264 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2004452639 Aug 09 07:53:27 PM PDT 24 Aug 09 07:54:02 PM PDT 24 731348400 ps
T1127 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4283668783 Aug 09 07:53:05 PM PDT 24 Aug 09 07:53:19 PM PDT 24 48851300 ps
T284 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1278566564 Aug 09 07:53:35 PM PDT 24 Aug 09 07:53:49 PM PDT 24 17232300 ps
T342 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.84996147 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:45 PM PDT 24 15686300 ps
T117 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.344810597 Aug 09 07:53:29 PM PDT 24 Aug 09 08:08:18 PM PDT 24 1359603600 ps
T1128 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3705456715 Aug 09 07:53:18 PM PDT 24 Aug 09 07:53:34 PM PDT 24 17423800 ps
T243 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.391950974 Aug 09 07:53:16 PM PDT 24 Aug 09 07:53:46 PM PDT 24 56137500 ps
T345 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.4251883042 Aug 09 07:53:12 PM PDT 24 Aug 09 07:53:25 PM PDT 24 42924400 ps
T1129 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2870122366 Aug 09 07:53:37 PM PDT 24 Aug 09 07:53:53 PM PDT 24 14695600 ps
T240 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3370105091 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:49 PM PDT 24 113514000 ps
T241 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.686675519 Aug 09 07:53:10 PM PDT 24 Aug 09 07:53:27 PM PDT 24 197951800 ps
T343 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3440717579 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:47 PM PDT 24 55301900 ps
T344 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3858811049 Aug 09 07:53:44 PM PDT 24 Aug 09 07:53:58 PM PDT 24 17045400 ps
T1130 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.465003062 Aug 09 07:53:10 PM PDT 24 Aug 09 07:53:26 PM PDT 24 19617100 ps
T265 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2708357350 Aug 09 07:53:30 PM PDT 24 Aug 09 07:53:43 PM PDT 24 32251500 ps
T1131 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1076741229 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:48 PM PDT 24 56406700 ps
T1132 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2576591206 Aug 09 07:53:38 PM PDT 24 Aug 09 07:53:54 PM PDT 24 47654700 ps
T242 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1574495682 Aug 09 07:53:23 PM PDT 24 Aug 09 07:53:41 PM PDT 24 47143300 ps
T1133 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1045484630 Aug 09 07:53:19 PM PDT 24 Aug 09 07:53:32 PM PDT 24 19930200 ps
T320 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1030532990 Aug 09 07:53:31 PM PDT 24 Aug 09 07:54:40 PM PDT 24 2834497500 ps
T253 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2583587211 Aug 09 07:53:18 PM PDT 24 Aug 09 07:53:37 PM PDT 24 259043000 ps
T266 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.435593177 Aug 09 07:53:20 PM PDT 24 Aug 09 07:53:37 PM PDT 24 63721900 ps
T1134 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2067144884 Aug 09 07:53:28 PM PDT 24 Aug 09 07:53:41 PM PDT 24 17801200 ps
T1135 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2351697918 Aug 09 07:53:15 PM PDT 24 Aug 09 07:53:31 PM PDT 24 15692000 ps
T267 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1855694916 Aug 09 07:53:11 PM PDT 24 Aug 09 07:53:28 PM PDT 24 61838300 ps
T254 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2359284219 Aug 09 07:53:24 PM PDT 24 Aug 09 07:53:44 PM PDT 24 854062800 ps
T346 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3145769266 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:45 PM PDT 24 78233900 ps
T347 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2524125372 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:47 PM PDT 24 14773400 ps
T1136 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.134070326 Aug 09 07:53:38 PM PDT 24 Aug 09 07:53:54 PM PDT 24 19920400 ps
T255 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1101341647 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:49 PM PDT 24 231336000 ps
T349 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2284233994 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:46 PM PDT 24 18018600 ps
T268 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.327349254 Aug 09 07:53:28 PM PDT 24 Aug 09 07:53:46 PM PDT 24 75266600 ps
T259 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1794885988 Aug 09 07:53:31 PM PDT 24 Aug 09 07:59:58 PM PDT 24 692746200 ps
T256 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.674534744 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:51 PM PDT 24 150397500 ps
T269 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.870831037 Aug 09 07:53:30 PM PDT 24 Aug 09 07:53:47 PM PDT 24 117098000 ps
T348 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2132855641 Aug 09 07:53:19 PM PDT 24 Aug 09 07:53:33 PM PDT 24 15572400 ps
T1137 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2178757455 Aug 09 07:53:25 PM PDT 24 Aug 09 07:53:55 PM PDT 24 19864000 ps
T257 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1445667739 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:51 PM PDT 24 147038600 ps
T294 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2958243938 Aug 09 07:53:12 PM PDT 24 Aug 09 08:00:53 PM PDT 24 176539700 ps
T1138 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3548544212 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:45 PM PDT 24 116462600 ps
T1139 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.124235012 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:46 PM PDT 24 32930400 ps
T1140 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3566770661 Aug 09 07:53:19 PM PDT 24 Aug 09 07:53:33 PM PDT 24 48578900 ps
T270 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2639714798 Aug 09 07:53:35 PM PDT 24 Aug 09 07:53:52 PM PDT 24 65377900 ps
T1141 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.154946807 Aug 09 07:53:36 PM PDT 24 Aug 09 07:53:50 PM PDT 24 63658100 ps
T1142 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2841929873 Aug 09 07:53:35 PM PDT 24 Aug 09 07:53:51 PM PDT 24 41367100 ps
T258 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.4031990276 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:51 PM PDT 24 176703300 ps
T289 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2367222530 Aug 09 07:53:32 PM PDT 24 Aug 09 08:08:25 PM PDT 24 655955300 ps
T1143 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1112347329 Aug 09 07:53:09 PM PDT 24 Aug 09 07:53:23 PM PDT 24 28853300 ps
T271 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.41476187 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:50 PM PDT 24 26737200 ps
T350 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.810798709 Aug 09 07:53:37 PM PDT 24 Aug 09 07:53:51 PM PDT 24 16477300 ps
T1144 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2965577797 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:48 PM PDT 24 41905900 ps
T290 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3716396098 Aug 09 07:53:34 PM PDT 24 Aug 09 08:08:28 PM PDT 24 4634187500 ps
T272 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.839831990 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:47 PM PDT 24 63414600 ps
T1145 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2792629791 Aug 09 07:53:16 PM PDT 24 Aug 09 07:53:32 PM PDT 24 11793500 ps
T1146 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2065300019 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:48 PM PDT 24 52705100 ps
T1147 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1030406106 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:51 PM PDT 24 262609700 ps
T1148 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2447656716 Aug 09 07:53:18 PM PDT 24 Aug 09 07:54:20 PM PDT 24 5126512200 ps
T1149 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1425403334 Aug 09 07:53:38 PM PDT 24 Aug 09 07:53:52 PM PDT 24 16790500 ps
T1150 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1997206757 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:50 PM PDT 24 57816300 ps
T1151 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3975289880 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:44 PM PDT 24 15405500 ps
T277 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2854662326 Aug 09 07:53:35 PM PDT 24 Aug 09 07:53:52 PM PDT 24 98153700 ps
T1152 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1253217571 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:49 PM PDT 24 65407600 ps
T1153 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1100694217 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:52 PM PDT 24 89240900 ps
T291 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1809607907 Aug 09 07:53:26 PM PDT 24 Aug 09 07:53:46 PM PDT 24 120359800 ps
T1154 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4010297679 Aug 09 07:53:22 PM PDT 24 Aug 09 07:53:40 PM PDT 24 79881400 ps
T1155 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2424810007 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:48 PM PDT 24 318894800 ps
T1156 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2735382595 Aug 09 07:53:37 PM PDT 24 Aug 09 07:53:57 PM PDT 24 316985500 ps
T1157 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2102047188 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:53 PM PDT 24 329438800 ps
T1158 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3219839781 Aug 09 07:53:36 PM PDT 24 Aug 09 07:53:49 PM PDT 24 13888400 ps
T1159 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3342764689 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:46 PM PDT 24 44313700 ps
T1160 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2307344715 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:46 PM PDT 24 24693800 ps
T1161 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.418377853 Aug 09 07:52:53 PM PDT 24 Aug 09 07:53:08 PM PDT 24 27657900 ps
T1162 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1234038456 Aug 09 07:53:07 PM PDT 24 Aug 09 07:53:20 PM PDT 24 13705300 ps
T1163 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3643976863 Aug 09 07:53:11 PM PDT 24 Aug 09 07:53:25 PM PDT 24 47266400 ps
T1164 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2879725396 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:43 PM PDT 24 154029000 ps
T1165 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.364387421 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:43 PM PDT 24 14379200 ps
T286 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.469592084 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:45 PM PDT 24 122734600 ps
T1166 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.61349481 Aug 09 07:52:56 PM PDT 24 Aug 09 07:54:07 PM PDT 24 2279856700 ps
T285 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3012147146 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:46 PM PDT 24 1797818900 ps
T293 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.368448286 Aug 09 07:53:32 PM PDT 24 Aug 09 08:01:11 PM PDT 24 436590100 ps
T361 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3550170032 Aug 09 07:53:35 PM PDT 24 Aug 09 08:00:01 PM PDT 24 425144700 ps
T260 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1541762874 Aug 09 07:53:23 PM PDT 24 Aug 09 07:53:37 PM PDT 24 28293700 ps
T1167 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3284186280 Aug 09 07:53:25 PM PDT 24 Aug 09 07:53:41 PM PDT 24 21518000 ps
T278 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2167686879 Aug 09 07:53:30 PM PDT 24 Aug 09 07:53:46 PM PDT 24 73027200 ps
T363 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1874517517 Aug 09 07:53:08 PM PDT 24 Aug 09 08:05:40 PM PDT 24 1450384800 ps
T1168 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3177961613 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:48 PM PDT 24 13063500 ps
T1169 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3256335428 Aug 09 07:53:24 PM PDT 24 Aug 09 07:53:40 PM PDT 24 41007400 ps
T295 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1057805619 Aug 09 07:53:27 PM PDT 24 Aug 09 08:08:36 PM PDT 24 2154195700 ps
T321 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3512973846 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:51 PM PDT 24 58946200 ps
T1170 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.614268100 Aug 09 07:53:28 PM PDT 24 Aug 09 07:53:45 PM PDT 24 1538618700 ps
T1171 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1372497026 Aug 09 07:53:30 PM PDT 24 Aug 09 07:53:49 PM PDT 24 58906000 ps
T1172 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1504639309 Aug 09 07:53:35 PM PDT 24 Aug 09 07:53:52 PM PDT 24 235168600 ps
T322 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3336280083 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:50 PM PDT 24 70360300 ps
T323 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2956669819 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:49 PM PDT 24 376865900 ps
T1173 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.91930681 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:43 PM PDT 24 32915800 ps
T1174 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2353654589 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:48 PM PDT 24 17346300 ps
T326 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3895532793 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:47 PM PDT 24 39154300 ps
T324 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3354393847 Aug 09 07:53:10 PM PDT 24 Aug 09 08:08:00 PM PDT 24 862566600 ps
T1175 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4289810726 Aug 09 07:53:06 PM PDT 24 Aug 09 07:53:40 PM PDT 24 337351200 ps
T328 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4099209484 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:46 PM PDT 24 38028900 ps
T1176 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.185981410 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:45 PM PDT 24 16356300 ps
T1177 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2262647310 Aug 09 07:53:27 PM PDT 24 Aug 09 07:53:46 PM PDT 24 227488200 ps
T1178 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3804352407 Aug 09 07:53:30 PM PDT 24 Aug 09 07:53:51 PM PDT 24 292101500 ps
T1179 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1783358638 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:45 PM PDT 24 87941500 ps
T327 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3953248978 Aug 09 07:53:23 PM PDT 24 Aug 09 07:53:40 PM PDT 24 258250500 ps
T362 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2841606335 Aug 09 07:53:35 PM PDT 24 Aug 09 08:08:38 PM PDT 24 1371907000 ps
T1180 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3013324949 Aug 09 07:53:45 PM PDT 24 Aug 09 07:54:03 PM PDT 24 768980500 ps
T1181 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1671432839 Aug 09 07:53:16 PM PDT 24 Aug 09 07:53:32 PM PDT 24 92048300 ps
T1182 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.711004768 Aug 09 07:53:35 PM PDT 24 Aug 09 07:53:48 PM PDT 24 14888100 ps
T325 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.699738353 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:48 PM PDT 24 188111600 ps
T1183 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3940159777 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:45 PM PDT 24 17037700 ps
T1184 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3092543469 Aug 09 07:53:38 PM PDT 24 Aug 09 07:53:51 PM PDT 24 25867400 ps
T1185 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2545167162 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:51 PM PDT 24 65853500 ps
T1186 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4129748482 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:46 PM PDT 24 16334600 ps
T1187 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3974395430 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:47 PM PDT 24 46224800 ps
T1188 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3649134204 Aug 09 07:53:27 PM PDT 24 Aug 09 07:53:43 PM PDT 24 93940200 ps
T1189 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.799475451 Aug 09 07:53:35 PM PDT 24 Aug 09 07:53:49 PM PDT 24 15039200 ps
T1190 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3066880302 Aug 09 07:53:20 PM PDT 24 Aug 09 07:54:13 PM PDT 24 1209374600 ps
T1191 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.307410421 Aug 09 07:53:31 PM PDT 24 Aug 09 08:00:00 PM PDT 24 705627700 ps
T1192 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3420983674 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:44 PM PDT 24 13160400 ps
T1193 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2128638172 Aug 09 07:53:30 PM PDT 24 Aug 09 07:53:46 PM PDT 24 12759400 ps
T1194 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.403812857 Aug 09 07:53:16 PM PDT 24 Aug 09 07:53:33 PM PDT 24 24276300 ps
T1195 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1096686485 Aug 09 07:53:16 PM PDT 24 Aug 09 07:54:39 PM PDT 24 3207310700 ps
T1196 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2250204680 Aug 09 07:53:37 PM PDT 24 Aug 09 07:53:51 PM PDT 24 16613000 ps
T1197 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2836134002 Aug 09 07:53:39 PM PDT 24 Aug 09 07:53:53 PM PDT 24 21995400 ps
T1198 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3117263762 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:47 PM PDT 24 46978500 ps
T329 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3625226318 Aug 09 07:53:14 PM PDT 24 Aug 09 07:53:54 PM PDT 24 96275200 ps
T1199 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1563940219 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:50 PM PDT 24 40589800 ps
T1200 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1498088631 Aug 09 07:53:16 PM PDT 24 Aug 09 07:53:32 PM PDT 24 67521100 ps
T1201 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.909854643 Aug 09 07:53:23 PM PDT 24 Aug 09 07:54:09 PM PDT 24 156313600 ps
T1202 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2110218055 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:50 PM PDT 24 127680600 ps
T1203 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2781568346 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:43 PM PDT 24 72800000 ps
T1204 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3670035384 Aug 09 07:53:11 PM PDT 24 Aug 09 07:53:24 PM PDT 24 110674700 ps
T330 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3259429687 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:53 PM PDT 24 200918400 ps
T1205 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3350118476 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:48 PM PDT 24 35211300 ps
T1206 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3841127233 Aug 09 07:53:19 PM PDT 24 Aug 09 07:53:34 PM PDT 24 18912800 ps
T1207 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2951713005 Aug 09 07:52:55 PM PDT 24 Aug 09 07:53:14 PM PDT 24 192308600 ps
T1208 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.131414363 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:47 PM PDT 24 81718700 ps
T331 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1411161937 Aug 09 07:53:01 PM PDT 24 Aug 09 07:54:06 PM PDT 24 6522177900 ps
T1209 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1888781729 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:47 PM PDT 24 31038200 ps
T1210 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1454467525 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:50 PM PDT 24 33299900 ps
T1211 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3468420491 Aug 09 07:53:25 PM PDT 24 Aug 09 07:53:43 PM PDT 24 298977700 ps
T1212 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3131069085 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:50 PM PDT 24 159019000 ps
T1213 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3397640559 Aug 09 07:53:28 PM PDT 24 Aug 09 07:53:44 PM PDT 24 19863000 ps
T1214 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.375554014 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:49 PM PDT 24 128844400 ps
T1215 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3571671718 Aug 09 07:53:11 PM PDT 24 Aug 09 07:53:29 PM PDT 24 133769700 ps
T288 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1702694659 Aug 09 07:53:38 PM PDT 24 Aug 09 07:53:54 PM PDT 24 64880300 ps
T1216 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1437366890 Aug 09 07:53:37 PM PDT 24 Aug 09 07:53:55 PM PDT 24 82681400 ps
T1217 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3223965422 Aug 09 07:53:37 PM PDT 24 Aug 09 07:53:51 PM PDT 24 49626300 ps
T1218 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1934775659 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:43 PM PDT 24 11656600 ps
T332 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3762857715 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:50 PM PDT 24 573874700 ps
T1219 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2131678253 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:43 PM PDT 24 50713900 ps
T1220 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.578092886 Aug 09 07:53:25 PM PDT 24 Aug 09 07:54:16 PM PDT 24 1652400600 ps
T1221 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.187535112 Aug 09 07:53:24 PM PDT 24 Aug 09 07:54:38 PM PDT 24 2398324900 ps
T279 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.4103603169 Aug 09 07:53:30 PM PDT 24 Aug 09 07:53:47 PM PDT 24 42211800 ps
T1222 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2777582711 Aug 09 07:53:11 PM PDT 24 Aug 09 07:53:27 PM PDT 24 14920500 ps
T296 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1335383719 Aug 09 07:53:30 PM PDT 24 Aug 09 08:01:10 PM PDT 24 373442800 ps
T1223 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3262892283 Aug 09 07:53:35 PM PDT 24 Aug 09 08:00:01 PM PDT 24 256699700 ps
T1224 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3675776173 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:45 PM PDT 24 16019100 ps
T1225 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3687287125 Aug 09 07:53:26 PM PDT 24 Aug 09 07:53:40 PM PDT 24 23004700 ps
T280 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2093002768 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:49 PM PDT 24 295289600 ps
T360 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3299767516 Aug 09 07:53:29 PM PDT 24 Aug 09 08:06:11 PM PDT 24 825600200 ps
T1226 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.889871092 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:53 PM PDT 24 331402200 ps
T1227 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.996444686 Aug 09 07:53:30 PM PDT 24 Aug 09 07:53:43 PM PDT 24 20599800 ps
T1228 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.662806059 Aug 09 07:53:13 PM PDT 24 Aug 09 07:53:30 PM PDT 24 37007100 ps
T261 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1804571982 Aug 09 07:53:11 PM PDT 24 Aug 09 07:53:24 PM PDT 24 93524300 ps
T1229 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3709064791 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:46 PM PDT 24 246555600 ps
T262 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1473133322 Aug 09 07:53:08 PM PDT 24 Aug 09 07:53:21 PM PDT 24 62683900 ps
T1230 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1436826075 Aug 09 07:53:23 PM PDT 24 Aug 09 07:53:37 PM PDT 24 17619300 ps
T1231 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2389678905 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:47 PM PDT 24 31640500 ps
T263 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.177470665 Aug 09 07:52:54 PM PDT 24 Aug 09 07:53:08 PM PDT 24 52791200 ps
T1232 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2878504165 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:45 PM PDT 24 55807300 ps
T1233 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3551887192 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:46 PM PDT 24 25385000 ps
T1234 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2315507197 Aug 09 07:53:35 PM PDT 24 Aug 09 07:53:51 PM PDT 24 12933700 ps
T1235 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.717665809 Aug 09 07:53:07 PM PDT 24 Aug 09 07:53:23 PM PDT 24 237285200 ps
T1236 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1153526039 Aug 09 07:53:16 PM PDT 24 Aug 09 07:53:32 PM PDT 24 52385500 ps
T292 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2670586073 Aug 09 07:53:23 PM PDT 24 Aug 09 07:53:42 PM PDT 24 53247300 ps
T1237 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2366287339 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:42 PM PDT 24 43195700 ps
T1238 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2580213864 Aug 09 07:53:36 PM PDT 24 Aug 09 07:53:49 PM PDT 24 164265000 ps
T1239 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2863027914 Aug 09 07:53:30 PM PDT 24 Aug 09 07:53:44 PM PDT 24 26220900 ps
T1240 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2853077148 Aug 09 07:53:20 PM PDT 24 Aug 09 07:53:34 PM PDT 24 19362100 ps
T287 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1503611067 Aug 09 07:53:28 PM PDT 24 Aug 09 07:53:45 PM PDT 24 135431500 ps
T1241 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1838693364 Aug 09 07:53:33 PM PDT 24 Aug 09 07:53:49 PM PDT 24 17697300 ps
T1242 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1546042928 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:43 PM PDT 24 30294500 ps
T1243 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1199804489 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:50 PM PDT 24 74182800 ps
T1244 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2241432991 Aug 09 07:53:20 PM PDT 24 Aug 09 07:53:56 PM PDT 24 629101800 ps
T1245 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1690264968 Aug 09 07:53:23 PM PDT 24 Aug 09 07:54:10 PM PDT 24 77038000 ps
T1246 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3804699305 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:46 PM PDT 24 35988500 ps
T1247 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.336520122 Aug 09 07:52:51 PM PDT 24 Aug 09 07:53:08 PM PDT 24 48661100 ps
T1248 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1606942081 Aug 09 07:53:31 PM PDT 24 Aug 09 07:53:46 PM PDT 24 92823100 ps
T1249 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.243562038 Aug 09 07:53:32 PM PDT 24 Aug 09 07:53:46 PM PDT 24 14068500 ps
T365 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.580825849 Aug 09 07:53:32 PM PDT 24 Aug 09 08:01:10 PM PDT 24 359345900 ps
T1250 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.512993210 Aug 09 07:53:34 PM PDT 24 Aug 09 07:53:48 PM PDT 24 55375200 ps
T1251 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.875128372 Aug 09 07:53:29 PM PDT 24 Aug 09 07:53:43 PM PDT 24 30773900 ps
T1252 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3865085516 Aug 09 07:53:20 PM PDT 24 Aug 09 07:53:34 PM PDT 24 71362600 ps
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