Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	298585	1		T1	2		T2	1506		T3	2
all_values[1]	298585	1		T1	2		T2	1506		T3	2
all_values[2]	298585	1		T1	2		T2	1506		T3	2
all_values[3]	298585	1		T1	2		T2	1506		T3	2
all_values[4]	298585	1		T1	2		T2	1506		T3	2
all_values[5]	298585	1		T1	2		T2	1506		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	603599	1		T1	12		T2	3012		T3	12
auto[1]	1187911	1		T2	6024		T4	54744		T17	5968

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	875530	1		T1	7		T2	4519		T3	7
auto[1]	915980	1		T1	5		T2	4517		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	298426	1		T1	2		T2	1506		T3	2
all_values[0]	auto[1]	auto[1]	159	1		T244	6		T245	2		T246	5
all_values[1]	auto[0]	auto[1]	298435	1		T1	2		T2	1506		T3	2
all_values[1]	auto[1]	auto[1]	150	1		T244	7		T245	1		T246	1
all_values[2]	auto[0]	auto[0]	1622	1		T1	2		T3	2		T4	1
all_values[2]	auto[0]	auto[1]	52	1		T244	1		T245	2		T246	1
all_values[2]	auto[1]	auto[0]	296848	1		T2	1506		T4	13686		T17	1492
all_values[2]	auto[1]	auto[1]	63	1		T244	2		T246	1		T298	1
all_values[3]	auto[0]	auto[0]	1644	1		T1	2		T3	2		T4	1
all_values[3]	auto[0]	auto[1]	59	1		T244	2		T245	1		T246	2
all_values[3]	auto[1]	auto[0]	90623	1		T2	1506		T4	353		T17	194
all_values[3]	auto[1]	auto[1]	206259	1		T4	13333		T17	1298		T38	1144
all_values[4]	auto[0]	auto[0]	1149	1		T1	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	543	1		T1	1		T3	1		T6	1
all_values[4]	auto[1]	auto[0]	185212	1		T2	1		T4	12019		T17	1238
all_values[4]	auto[1]	auto[1]	111681	1		T2	1505		T4	1667		T17	254
all_values[5]	auto[0]	auto[0]	1584	1		T1	2		T3	2		T4	1
all_values[5]	auto[0]	auto[1]	85	1		T7	1		T20	1		T39	1
all_values[5]	auto[1]	auto[0]	296848	1		T2	1506		T4	13686		T17	1492
all_values[5]	auto[1]	auto[1]	68	1		T244	2		T246	2		T298	1